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HY64LD16162M-DF85I Datasheet(PDF) 6 Page - Hynix Semiconductor |
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HY64LD16162M-DF85I Datasheet(HTML) 6 Page - Hynix Semiconductor |
6 / 11 page HY64LD16162M Series 6 Revision 1.7 March. 2002 STANDBY MODE CHARACTERISTICS Mode Memory Cell Data Standby Current[ µA] Wait Time[ µs] Standby Valid 75 0 Deep Power Down Invalid 2 200 STATE DIAGRAM 1. Supply power. 2. Maintain stable power for longer than 200 µs. Power-Up Sequence 1. Keep CS2 low state. Deep power down mode is maintained while CS2 is low state. Deep Power Down Entry Sequence 1. Keep CS2 high state. 2. Maintain stable power for longer than 200 µs. Deep Power Down Exit Sequence Power On Power On Power On Wait 200 µs Wait 200 Wait 200 µµss Active Active Active Standby Mode Standby Standby Mode Mode Deep Power Down Mode Deep Power Deep Power Down Mode Down Mode / CS1=VIL, CS2=VIH, /UB&/LB ≠VIH CS2=VIL CS2=VIL CS2=VIH, /CS1=VIH or /UB,/LB=VIH Deep Power Down Entry Sequence CS2=VIH |
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