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HY64UD16162B-E Datasheet(PDF) 7 Page - Hynix Semiconductor |
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HY64UD16162B-E Datasheet(HTML) 7 Page - Hynix Semiconductor |
7 / 11 page HY64UD16162B Series 7 Revision 1.0 / December. 2002 Notes : 1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status. 2. /OE = VIL 3. tCHZ, tBHZ and tOHZ are defined as the time at which the outputs achieve the high impedance state and tOLZ,tBLZ and tCLZ are defined as the time at which the outputs achieve the low impedance state. These are not referenced to output voltage levels. 4. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active. TIMING DIAGRAM READ CYCLE 1 ( Note 1, 4 ) ADD /CS1 CS2 /UB, /LB /OE Data Out High-Z Vih tRC tAA tACS tBA tOE tOLZ(3) tBLZ(3) tCLZ(3) tOH tCHZ(3) tBHZ(3) tOHZ(3) Data Valid READ CYCLE 2 ( Note 1, 2, 4 )( CS2=Vih ) ADD Data Out Data Valid tRC Previous Data tOH tAA tOH READ CYCLE 3 ( Note 1, 2, 4 )( CS2=Vih ) /CS1 /UB, /LB Data Out Data Valid High-Z tCLZ(3) tACS tCHZ(3) |
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