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HY64UD16162M-DF85E Datasheet(PDF) 8 Page - Hynix Semiconductor |
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HY64UD16162M-DF85E Datasheet(HTML) 8 Page - Hynix Semiconductor |
8 / 11 page HY64UD16162M Series 8 Revision 1.7 March. 2002 Notes : 1. A write occurs during the overlap of low /CS1, low /WE and low /UB and/or /LB. 2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS1, /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. /OE is continuously low (/OE=VIL) 6. Q(data out) is the invalid data. 7. Q(data out) is the read data of the next address. 8. tWHZ is defined as the time at which the outputs achieve the high impedance state. It is not referenced to output voltage levels. 9. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active. 10. Do not input data to the I/O pins while they are in the output state. WRITE CYCLE 1 ( Note 1, 4, 5, 9, 10 ) ( /WE Controlled ) ADD /CS1 CS2 /UB, /LB /WE Data Out Data In Vih tWC tCW tBW tWP tWR(2) Data Valid tAW tAS High-Z tDW tDH tWHZ(3,8) tOW (6) (7) WRITE CYCLE 2 ( Note 1, 4, 5, 9, 10 ) ( /CS1 Controlled ) ADD /CS1 CS2 /UB, /LB /WE Data Out Data In Vih tWC tCW tBW tWP tWR(2) Data Valid tAW High-Z tDW tDH High-Z tAS |
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Similar Description - HY64UD16162M-DF85E |
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