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LXT300Z Datasheet(PDF) 10 Page - Level One |
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LXT300Z Datasheet(HTML) 10 Page - Level One |
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10 / 20 page  ëðìí /;7êíí= î /;7êíì= $GYDQFHG 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHUV L1 $33/,&$7,21 ,1)250$7,21 /;7êíí= +RVW 0RGH ìïèéé 0ESV 7ì ,QWHUIDFH $SSOLFDWLRQ Figure 5 is a typical 1.544 Mbps T1 application. The LXT300Z is shown in the Host Mode with a typical T1/ ESF framer providing the digital interface with the host controller. Both devices are controlled through the serial interface. An LXP600A Clock Adapter (CLAD) provides the 2.048 MHz system backplane clock, locked to the recovered 1.544 MHz clock signal. The power supply inputs are tied to a common bus with appropriate decou- pling capacitors installed (68 µF on the transmit side, 1.0 µF and 0.1 µF on the receive side). )LJXUH èã 7\SLFDO /;7êíí= ìïèéé 0ESV 7ì $SSOLFDWLRQ õ+RVW 0RGHô 72 +267 &21752//(5 7ì (6) )5$0(5 ìïèéé 0+] &/2&. 9ò /;3çíí$îçíë &/$' &/., )6, &/.2 ëïíéå 0+] çïìæç 0+] ëë . Ω í9 ì µ) 7ì /,1( 5(&(,9( ìãìãì ìãë ìïèéé 0+] 7ì /,1( 75$160,7 íïéæ µ) µ) çå 121ð 32/$5,=(' &/.( 6&/. &6 6'2 6', ,17 5*1' 59ò 55,1* 57,3 05,1* 07,3 75,1* 79ò /;7êíí= 75$16&(,9(5 ò9 ëëí Ω ò9 ëëí Ω 706<1& &6 6'2 ,17 6&/. 6', 7)6<1& 7&/. 7326 71(* 636 51(* 5326 5&/. 0&/. 7&/. 7326 71(* 02'( 51(* 5326 5&/. ;7$/,1 ;7$/287 '30 /26 77,3 7*1' íïì µ) 127( ì 127( ë 127( ì 7+( /;7êíí= ,6 &203$7,%/( :,7+ $ :,'( 9$5,(7< 2) ',*,7$/ )5$0,1* $1' 6,*1$/,1* '(9,&(6ñ ,1&/8',1* 7+( '6ëìåì$ñ '6ëìåí$ñ 07åäæçñ $1' 5åíæíï 127( ë :+(1 /;7êíí= ,6 &211(&7(' 72 7+( &5266ð&211(&7 )5$0( 7+528*+ $ /2: /(9(/ 021,725 -$&.ñ 5(&(,9( 75$16)250(5 6+28/' %(ìãëãë72 %2267 7+( ,1387 6,*1$/ï ìïèéé 0+] |
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