VRS51x550/560
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Structure of Port 0
The internal structure of P0 is shown below. The
auxiliary function of this port requires a particular logic.
As opposed to the other ports, P0 is truly bi-directional.
In other words, when used as an input, it is considered
to be in a floating logical state (high impedance state).
This arises from the absence of the internal pull-up
resistance. The pull-up resistance is actually replaced
by a transistor that is only used when the port is
configured to access the external memory/data bus
(EA=0).
When used as an I/O port, P0 acts as an open drain
port and the use of an external pull-up resistor is likely
to be required for most applications.
FIGURE 8: PORT P0’S PARTICULAR STRUCTURE
D Flip-Flop
Q
Q
IC Pin
Read Register
Internal Bus
Write to
Register
Read Pin
X1
Control
Address A0/A7
Vcc
When P0 is used as an external memory bus input (for
a MOVX instruction, for example), the outputs of the
register are automatically forced to 1.
Port P0 and P2 as Address and Data Bus
The output stage may receive data from two sources:
•
The outputs of register P0 or the bus address
itself multiplexed with the data bus for P0
•
The outputs of the P2 register or the high byte
(A8 through A15) of the bus address for the P2
port
FIGURE 9: P2 PORT STRUCTURE
D Flip-Flop
Q
Q
IC Pin
Read Register
Internal Bus
Write to
Register
Read Pin
Vcc
Pull-up
Network
X1
Control
Address
When the ports are used as an address or data bus,
the
special
function
registers
P0
and
P2
are
disconnected from the output stage. The 8 bits of the
P0 register are forced to 1 and the content of the P2
register remains constant.
Auxiliary Port 1 Functions
The Port 1 I/O pins are shared with the T2EX and T2
inputs as shown below:
Pin
Mnemonic
Function
P1.0
T2
Timer 2 counter input
P1.1
T2EX
Timer 2 Auxiliary input
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
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