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IDT72T51553 Datasheet(PDF) 2 Page - Integrated Device Technology

Part # IDT72T51553
Description  2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72T51553 Datasheet(HTML) 2 Page - Integrated Device Technology

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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
DESCRIPTION:
The IDT72T51543/72T51553 multi-queue flow-control devices are single
chip within which anywhere between 1 and 32 discrete FIFO queues can be
setup.Allqueueswithinthedevicehaveacommondatainputbus,(writeport)
and a common data output bus, (read port). Data written into the write port is
directed to a respective queue via an internal de-multiplex operation, ad-
dressedbytheuser.Datareadfromthereadportisaccessedfromarespective
queue via an internal multiplex operation, addressed by the user. Data writes
and reads can be performed at high speeds up to 200MHz, with access times
of3.6ns.Datawriteandreadoperationsaretotallyindependentofeachother,
a queue maybe selected on the write port and a different queue on the read
port or both ports may select the same queue simultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
AlmostFullandProgrammableAlmostEmptyflagforeachqueueisprovided.
Two8bitprogrammableflagbussesareavailable,providingstatusofqueues
notselectedforwriteorreadoperations.When8orlessqueuesareconfigured
in the device these flag busses provide an individual flag per queue, when
more than 8 queues are used, either a Polled or Direct mode of bus operation
provides the flag busses with all queues status.
Bus Matching is available on this device, either port can be 9 bits or 18 bits
wide. When Bus Matching is used the device ensures the logical transfer of
data throughput in a Little Endian manner.
The user has full flexibility configuring queues within the device, being able
toprogramthetotalnumberofqueuesbetween1and32,theindividualqueue
depthsbeingindependentofeachother.Theprogrammableflagpositionsare
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
BothMasterResetandPartialResetpinsareprovidedonthisdevice.AMaster
Reset latches in all configuration setup pins and must be performed before
programmingofthedevicecantakeplace.APartialResetwillresetthereadand
writepointersofanindividualqueue,providedthatthequeueisselectedonboth
the write port and read port at the time of partial reset.
Echo Read Enable,
EREN and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the queue that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect to
ERENandERCLK,thisisveryusefulwhendataisbeingreadathigh
speed.
The multi-queue flow-control device has the capability of operating its IO in
either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected
via the IOSEL input. The core supply voltage (VCC) to the multi-queue is always
2.5V,howevertheoutputlevelscanbesetindependentlyviaaseparatesupply,
VDDQ.
The devices also provide additional power savings via a Power Down Input.
This input disables the write port data inputs when no write operations are
required.
AJTAGtestportisprovided,herethemulti-queuedevicehasafullyfunctional
BoundaryScanfeature,compliantwithIEEE1149.1StandardTestAccessPort
and Boundary Scan Architecture.
See Figure 1,Multi-Queue Flow-Control Device Block Diagramfor an outline
of the functional blocks within the device.


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