VRS51x570/580
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Input/Output Ports
The VRS51x570 and VRS51x580 have a total of 36 bi-
directional I/O lines grouped into four 8-bit I/O ports
and one 4-bit I/O port. These I/Os can be individually
configured as inputs or outputs.
With the exception of the P0 I/Os, which are of the
open drain type, each I/O is made of a transistor
connected to ground and a weak pull-up resistor.
Writing a 0 in a given I/O port bit register will activate
the transistor connected to Vss and bring the I/O to a
LOW level.
Writing a 1 into a given I/O port bit register de-activates
the transistor between the pin and ground. In this case
the pull-up resistor will bring the corresponding pin to a
HIGH level.
To use a given I/O as an input, a 1 must be written into
its associated port register bit. By default, upon reset
all I/Os are configured as inputs.
General Structure of an I/O Port
The following elements establish the link between the
core unit and the pins of the microcontroller:
•
Special Function Register (same name as port)
•
Output Stage Amplifier (the structure of this
element varies with its auxiliary function)
From the following figure, one can see that the D flip-
flop stores the value received from the internal bus
after receiving a write signal from the core. Also, note
that the Q output of the flip-flop can be linked to the
internal bus by executing a read instruction.
This is how one would read the content of the register.
It is also possible to link the value of the pin to the
internal bus. This is done by the “read pin” instruction.
In short, the user may read the value of the register or
the pin.
FIGURE 6: INTERNAL STRUCTURE OF ONE OF THE EIGHT I/O PORT LINES
D Flip-Flop
Output
Stage
Q
Q
IC Pin
Read Register
Internal Bus
Write to
Register
Read Pin
Structure of the P1, P2, P3 and P4
The following figure provides a general idea of the
structure of the P1, P2, P3 and P4 ports. Note that the
intermediary logic that connects the output of the
register and the output stage together is not shown
because this logic varies with the auxiliary function of
each port.
FIGURE 7: GENERAL STRUCTURE OF THE OUTPUT STAGE OF P1, P2 AND P3
D Flip-Flop
Q
Q
IC Pin
Read Register
Internal Bus
Write to
Register
Read Pin
Vcc
Pull-up
Network
X1
Each line may be used independently as a logical
input or output. When used as an input, as mentioned
earlier, the corresponding port register bit must be
high.
Structure of Port 0
The internal structure of P0 is shown below. The
auxiliary function of this port requires a particular logic.
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