VRS51x550/560
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page 8 of 40
Description of Peripherals
System Control Register
The SYSCON register is used for system control and is
described in the following table.
The WDRESET bit (7) indicates whether the system
has been reset due to overflow of the watchdog timer.
Bit 0 of the SYSCON register is the ALE output inhibit
bit. Setting this bit to 1 will inhibit the Fosc/6 clock
signal output to the ALE pin.
TABLE 8: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH
7
6
5
4
3
2
1
0
WDRESET
Unused
XRAME
ALEI
Bit
Mnemonic
Description
7
WDRESET
This is the watchdog timer reset bit. It
will be set to 1 when the reset signal
generated by WDT overflows.
6
Unused
-
5
Unused
-
4
Unused
-
3
Unused
-
2
Unused
-
1
Unused
-
0
ALEI
ALE output inhibit bit, which is used to
reduce EMI.
Power Control Register
VRS51x550/560 devices provide two power saving
modes: Idle and Power Down. These two modes serve
to reduce the power consumption of the device.
In Idle mode, the processor is stopped but the oscillator
continues to run. The contents of the RAM, I/O state
and SFR registers are maintained and the timer and
external interrupts are left operational. The processor
will be woken up when an external event, triggering an
interrupt, occurs.
In Power Down mode, the VRS51x550/560 oscillator
and peripherals are disabled. The contents of the RAM
and the SFR registers, however, are maintained.
The minimum VCC in Power Down mode is 2V.
These power saving modes are controlled by the
PDOWN and IDLE bits of the PCON register at
address 87h.
TABLE 9: POWER CONTROL REGISTER (PCON) - SFR 87H
7
6
5
4
3
2
1
0
Unused
RAM1
RAM0
Bit
Mnemonic
Description
7
SMOD
1: Double the baud rate of the serial port
frequency that was generated by Timer 1.
0: Normal serial port baud rate generated by
Timer 1.
6
5
4
3
GF1
General Purpose Flag
2
GF0
General Purpose Flag
1
PDOWN
Power Down mode control bit
0
IDLE
Idle mode control bit
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