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SN74GTL2006PWRE4 Datasheet(PDF) 3 Page - Texas Instruments |
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SN74GTL2006PWRE4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 10 page SN74GTL2006 13BIT GTL/GTL/GTL+ TO LVTTL TRANSLATOR SCES619 – DECEMBER 2004 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic symbol 2BI 1BI 10AI1 10AI2 GTL Input 11BI 11BO 10BO2 10BO1 4AO 3AO 2AO 1AO LVTTL I/Os 5BI 7BO1 1 2 3 4 5 6 26 25 24 22 21 20 19 17 16 15 8 9 10 11 12 13 SN74GTL2006 27 LVTTL Input 8AI GTL Input 9BI 7BO2 6BI 8BO 23 3BI 4BI 9AO LVTTL Output 7 GTL Outputs Delay Delay GTL Inputs GTL Inputs GTL Outputs LVTTL Outputs 5A (Open Drain) 6A (Open Drain) LVTTL I/O 11A (Open Drain) LVTTL Outputs LVTTL Inputs GTL VREF 18 NOTE A: The enable on 7BO1/7BO2 includes a delay that prevents a transient conditon (where 5BI/6BI go from low to high, and the low to high on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs. |
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