Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

CY7C1325G-117AXC Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1325G-117AXC
Description  4-Mbit (256K x 18) Flow-Through Sync SRAM
Download  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1325G-117AXC Datasheet(HTML) 9 Page - Cypress Semiconductor

Back Button CY7C1325G-117AXC Datasheet HTML 5Page - Cypress Semiconductor CY7C1325G-117AXC Datasheet HTML 6Page - Cypress Semiconductor CY7C1325G-117AXC Datasheet HTML 7Page - Cypress Semiconductor CY7C1325G-117AXC Datasheet HTML 8Page - Cypress Semiconductor CY7C1325G-117AXC Datasheet HTML 9Page - Cypress Semiconductor CY7C1325G-117AXC Datasheet HTML 10Page - Cypress Semiconductor CY7C1325G-117AXC Datasheet HTML 11Page - Cypress Semiconductor CY7C1325G-117AXC Datasheet HTML 12Page - Cypress Semiconductor CY7C1325G-117AXC Datasheet HTML 13Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 16 page
background image
CY7C1325G
Document #: 38-05518 Rev. *D
Page 9 of 16
Switching Characteristics Over the Operating Range [14, 15]
Parameter
Description
–133
–100
Unit
Min.
Max.
Min.
Max.
tPOWER
VDD(Typical) to the first Access
[10]
11
ms
Clock
tCYC
Clock Cycle Time
7.5
10
ns
tCH
Clock HIGH
2.5
4.0
ns
tCL
Clock LOW
2.5
4.0
ns
Output Times
tCDV
Data Output Valid After CLK Rise
6.5
8.0
ns
tDOH
Data Output Hold After CLK Rise
2.0
2.0
ns
tCLZ
Clock to Low-Z[11, 12, 13]
00
ns
tCHZ
Clock to High-Z[11, 12, 13]
3.5
3.5
ns
tOEV
OE LOW to Output Valid
3.5
3.5
ns
tOELZ
OE LOW to Output Low-Z[11, 12, 13]
00
ns
tOEHZ
OE HIGH to Output High-Z[11, 12, 13]
3.5
3.5
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.5
2.0
ns
tADS
ADSP, ADSC Set-up Before CLK Rise
1.5
2.0
ns
tADVS
ADV Set-up Before CLK Rise
1.5
2.0
ns
tWES
GW, BWE, BWX Set-up Before CLK Rise
1.5
2.0
ns
tDS
Data Input Set-up Before CLK Rise
1.5
2.0
ns
tCES
Chip Enable Set-up
1.5
2.0
ns
Hold Times
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.5
0.5
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Notes:
10. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
11. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested.
14. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.


Similar Part No. - CY7C1325G-117AXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1325G-133AXC CYPRESS-CY7C1325G-133AXC Datasheet
805Kb / 21P
   4-Mbit (256 K x 18) Flow through Sync SRAM Synchronous self timed write
CY7C1325G-133AXC CYPRESS-CY7C1325G-133AXC Datasheet
753Kb / 22P
   4-Mbit (256 K 횞 18) Flow-Through Sync SRAM
CY7C1325G-133AXC CYPRESS-CY7C1325G-133AXC Datasheet
769Kb / 23P
   4-Mbit (256 K x 18) Flow-Through Sync SRAM
More results

Similar Description - CY7C1325G-117AXC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1325F-117AC CYPRESS-CY7C1325F-117AC Datasheet
430Kb / 17P
   4-Mb (256K x 18) Flow-Through Sync SRAM
CY7C1365C CYPRESS-CY7C1365C Datasheet
400Kb / 18P
   9-Mbit (256K x 32) Flow-Through Sync SRAM
CY7C1325G CYPRESS-CY7C1325G_13 Datasheet
769Kb / 23P
   4-Mbit (256 K x 18) Flow-Through Sync SRAM
CY7C1327G CYPRESS-CY7C1327G Datasheet
340Kb / 18P
   4-Mbit (256K x 18) Pipelined Sync SRAM
CY7C1327G CYPRESS-CY7C1327G_06 Datasheet
373Kb / 18P
   4-Mbit (256K x 18) Pipelined Sync SRAM
CY7C1324H CYPRESS-CY7C1324H Datasheet
678Kb / 15P
   2-Mbit (128K x 18) Flow-Through Sync SRAM
CY7C1297H CYPRESS-CY7C1297H Datasheet
354Kb / 15P
   1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1297F CYPRESS-CY7C1297F Datasheet
439Kb / 15P
   1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1353G CYPRESS-CY7C1353G_07 Datasheet
575Kb / 13P
   4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture
CY7C1353G CYPRESS-CY7C1353G Datasheet
229Kb / 13P
   4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com