CY7C1325G-117AXI datasheet(10/16 Pages) CYPRESS

Part #	CY7C1325G-117AXI

Description	4-Mbit (256K x 18) Flow-Through Sync SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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10 / 16 page

CY7C1325G

Document #: 38-05518 Rev. *D

Page 10 of 16

Timing Diagrams

Read Cycle Timing[16]

Note:

16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

tCYC

t

CL

CLK

tADH

tADS

ADDRESS

t

CH

tAH

tAS

A1

tCEH

tCES

Data Out (Q)

High-Z

tCLZ

tDOH

tCDV

tOEHZ

tCDV

Single READ

BURST

READ

tOEV

tOELZ

tCHZ

Burst wraps around

to its initial state

t

ADVH

t

ADVS

t

WEH

t

WES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1)

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

A2

ADV suspends burst

Deselect Cycle

DON’T CARE

UNDEFINED

ADSP

ADSC

GW, BWE,BW

[A:B]

CE

ADV

OE

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