HY62256AJ-I datasheet(7/14 Pages) ETC

Part #	HY62256AJ-I

Description	DRAM & SRAM MEMORY

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AC CHARACTERISTICS

Vcc = 5V(±)10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.) unless otherwise

specified.

# Symbol

Parameter

-55

-70

-85

Unit

Min. Max. Min. Max. Min. Max.

READ CYCLE

1

tRC

Read Cycle Time

55

-

70

-

85

-

ns

2

tAA

Address Access Time

-

55

-

70

-

85

ns

3

tACS

Chip Select Access Time

-

55

-

70

-

85

ns

4

tOE

Output Enable to Output

Valid

-

30

-

35

-

45

ns

5

tCLZ

Chip Select to Output in

Low Z

5

-

5

-

5

-

ns

6

tOLZ

Output Enable to Output in

Low Z

5

-

5

-

5

-

ns

7

tCHZ

Chip Deselection to Output

in High Z

0

20

0

30

0

30

ns

8

tOHZ

Out Disable to Output in

High Z

0

20

0

30

0

30

ns

9

tOH

Output Hold from Address

Change

5

-

5

-

5

-

ns

WRITE CYCLE

10 tWC

Write Cycle Time

55

-

70

-

85

-

ns

11 tCW

Chip Selection to End of

Write

50

-

65

-

75

-

ns

12 tAW

Address Valid to End of

Write

50

-

65

-

75

-

ns

13 tAS

Address Set-up Time

0

-

0

-

0

-

ns

14 tWP

Write Pulse Width

40

-

50

-

55

-

ns

15 tWR

Write Recovery Time

0

-

0

-

0

-

ns

16 tWHZ

Write to Output in High Z

0

20

0

30

0

30

ns

17 tDW

Data to Write Time Overlap 25

-

35

-

40

-

ns

18 tDH

Data Hold from Write Time 0

-

0

-

0

-

ns

19 tOW

Output Active from End of

Write

5

-

5

-

5

-

ns

AC TEST CONDITIONS

TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.) unless otherwise specified.

PARAMETER

VALUE

Input Pulse Level

0.8V to 2.4V

Input Rise and Fall Time

5ns

Input and Output Timing Reference Levels

1.5V

Output Load

70/85/100ns

CL = 100pF + 1TTL Load

55ns

CL = 50pF + 1TTL Load

3 of 4

22/10/97 12:33

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http://www.hea.com/hean2/sram/62256ala1.htm

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