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ADSP-21266SKSTZ-2B Datasheet(PDF) 1 Page - Analog Devices |
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ADSP-21266SKSTZ-2B Datasheet(HTML) 1 Page - Analog Devices |
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1 / 44 page  SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. SHARC® Embedded Processor ADSP-21266 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com FAX: 781.461.3113 © 2004 Analog Devices, Inc. All rights reserved. SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs The ADSP-21266 processes high performance audio while enabling low system costs Audio decoders and post processor algorithms support: Nonvolatile memory can be configured to contain a combi- nation of PCM 96 kHz, Dolby® Digital, Dolby Digital Surround EX TM, DTS-ESTM Discrete 6.1, DTS-ES Matrix 6.1, DTS ® 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA- PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and DTS Neo:6 TM Various multichannel surround-sound decoders are con- tained in ROM. For configurations of decoder algorithms, see Table 2 on Page 6. Single-instruction multiple-data (SIMD) computational archi- tecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O—a parallel port, an SPI ® port, six serial ports, a digital audio interface (DAI), and JTAG DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisi- tion port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU) On-chip memory—2M bits of on-chip SRAM and a dedicated 4M bits of on-chip mask-programmable ROM The ADSP-21266 is available with a 150 MHz or a 200 MHz core instruction rate. For complete ordering information, see Ordering Guide on Page 44. Figure 1. Functional Block Diagram ADDR DATA PX REGI STER 6 JTAG TES T & EMULATION 20 3 SERIAL PORTS (6) INPUT DATA PORTS (8) PARALLEL DATA ACQUISITION PORT TIMERS (3) SI GNAL RO UTI NG UNI T PRECISI ON CLOCK GENERATORS (2) DIGITAL AUDIO INTERFACE 3 16 A DDRES S/ DATA BUS / GPIO CON TR OL/GPIO PARALLEL PORT IOP REGISTE RS (MEMORY MAPPED) CO NTROL, STATUS , DATA BUFFERS 4 SPI PORT (1) DMA CONTRO LLER 2 2 CHANNELS 4 GPIO FLAGS/ IRQ /TIMEXP PRO CESSI NG ELEMENT (PEY) PROCESSING ELEMENT (PEX) TIMER INSTRUCTION CACHE 32 48-BIT DAG1 8 4 32 DAG2 8 4 32 32 PM ADDRE SS BUS DM ADDRESS BUS PM DATA BUS DM DATA BUS 64 64 CORE PROCESSOR PROG RAM SEQ UE NCER ADDR DATA SRAM 1M BIT ROM 2M BI T DUAL PORTED MEMORY BLOCK 0 SRAM 1M BI T ROM 2M BIT DUAL PORTED MEMORY BLO CK 1 S IOD (32) IOA (18) 32 I/O PROCESSOR |
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