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2003 Integrated Device Technology, Inc.

All rights reserved. Product specifications subject to change without notice.

DSC-5609/4



NOVEMBER 2003

2,048 x 36 x 2

4,096 x 36 x 2

8,192 x 36 x 2

IDT723652

IDT723662

IDT723672

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

FEATURES

IDT723652

–

2,048 x 36 x 2

IDT723662

–

4,096 x 36 x 2

IDT723672

–

8,192 x 36 x 2

(simultaneous reading and writing of data on a single clock edge

is permitted)

tions

functions) or First Word Fall Through timing (using ORA, ORB, IRA

and IRB flag functions)

120-pin Thin Quad Flatpack (TQFP)

°°°°°C to +85°°°°°C) is available

DESCRIPTION

The IDT723652/723662/723672 is a monolithic, high-speed, low-power,

CMOS Bidirectional SyncFIFO (clocked) memories which support clock

frequencies up to 83MHz and have read access times as fast as 8ns. Two

independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs on board each

chipbufferdatainoppositedirections. Communicationbetweeneachportmay

bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has

a flag to signal when new mail has been stored.

FUNCTIONAL BLOCK DIAGRAM

Mail 1

Register

Programmable Flag

Offset Registers

RAM

ARRAY

2,048 x 36

4,096 x 36

8,192 x 36

Write

Pointer

Read

Pointer

Status Flag

Logic

Write

Pointer

Read

Pointer

Status Flag

Logic

CLKA

CSA

W/

RA

ENA

MBA

Port-A

Control

Logic

FIFO1,

Mail1

Reset

Logic

RST1

Mail 2

Register

MBF2

CLKB

CSB

W/RB

ENB

MBB

Port-B

Control

Logic

FIFO2,

Mail2

Reset

Logic

RST2

MBF1

FIFO 1

FIFO 2

13

EFB/ORB

AEB

36

36

FFB/IRB

AFB

FFA/IRA

AFA

EFA/ORA

AEA

5609 drw 01

36

36

Timing

Mode

FWFT

RAM

ARRAY

2,048 x 36

4,096 x 36

8,192 x 36