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IDT723652L12PF Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT723652L12PF Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 29 page  7 COMMERCIALTEMPERATURERANGE IDT723652/723662/723672 CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS) 0 10 20 3040 5060 70 0 50 100 150 200 250 300 VCC = 5.0V fS Clock Frequency MHz fdata = 1/2 fS TA = 25oC CL = 0 pF VCC = 4.5V VCC = 5.5V 5609 drw03a 80 90 Calculating Power Dissipation The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723652/723662/723672 with CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by: PT = VCC x [ICC(f) + (N x ÐICC x dc)] + Σ(CL x VCC2 X fo) where: N = number of inputs driven by TTL levels ∆ICC = increase in power supply current for each input at a TTL HIGH level dc = duty cycle of inputs at a TTL HIGH level of 3.4 V CL = outputcapacitanceload fo = switching frequency of an output |
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