Electronic Components Datasheet Search |
|
IDT723672L12PQF Datasheet(PDF) 10 Page - Integrated Device Technology |
|
IDT723672L12PQF Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 29 page 10 COMMERCIALTEMPERATURERANGE IDT723652/723662/723672 CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 read request necessary. Subsequent words must be accessed by performing a formal read operation. Following Reset, the level applied to the FWFTinputtochoosethedesired timing mode must remain static throughout FIFO operation. Refer to Figure 2 (Reset) for a First Word Fall Through select timing diagram. ALMOST-EMPTYFLAGANDALMOST-FULLFLAGOFFSETPROGRAMMING Four registers in these devices are used to hold the offset values for the Almost-EmptyandAlmost-Fullflags. TheportBAlmost-Emptyflag( AEB)Offset register is labeled X1 and the port A Almost-Empty flag ( AEA)Offsetregisteris labeled X2. The port A Almost-Full flag ( AFA)OffsetregisterislabeledY1and theportBAlmost-Fullflag( AFB)OffsetregisterislabeledY2. Theindexofeach register name corresponds to its FIFO number. The offset registers can be loadedwithpresetvaluesduringtheresetofaFIFOortheycanbeprogrammed from port A (see Table 1). FS0andFS1functionthesamewayinbothIDTStandardandFWFTmodes. — PRESET VALUES ToloadtheFIFO'sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith oneofthethreepresetvalueslistedinTable1,atleastoneoftheflagselectinputs mustbeHIGHduringtheLOW-to-HIGHtransitionofitsresetinput. Forexample, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be HIGH when FlFO1Reset( RST1)returnsHIGH. FlagoffsetregistersassociatedwithFIFO2 are loaded with one of the preset values in the same way with FIFO2 Reset ( RST2) toggled simultaneously with FIFO1 Reset (RST1). For preset value loading timing diagram, see Figure 2. — PARALLEL LOAD FROM PORT A To program the X1, X2, Y1, and Y2 registers from port A, both FlFOs should be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH transitionoftheResetinputs. Itisimportanttonotethatonceparallelprogramming hasbeenselectedduringaMasterResetbyholdingbothFS0&FS1LOW,these inputsmustremainLOWduringallsubsequentFIFOoperation. Theycanonly be toggled HIGH when future Master Resets are performed and other programming methods are desired. After this reset is complete, the first four writes to FIFO1 do not store data in the FIFO memory but load the offset registers in the order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are (A7-A0), (A8-A0), or (A9-A0) SIGNAL DESCRIPTION RESET After power up, a Master Reset operation must be performed by providing a LOW pulse to RST1 and RST2 simultaneously. Afterwards, the FIFO memories of the IDT723652/723662/723672 are reset separately by taking theirReset( RST1,RST2)inputsLOWforatleastfourport-AClock(CLKA)and four port-B Clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the Input Ready flag (IRA, IRB) LOW, the Output Ready flag (ORA, ORB) LOW, the Almost-Empty flag ( AEA, AEB) LOW, and theAlmost-Fullflag( AFA,AFB)HIGH. ResettingaFIFOalsoforcestheMailbox Flag( MBF1,MBF2)oftheparallelmailboxregisterHIGH. AfteraFIFOisreset, itsInputReadyflagissetHIGHaftertwoclockcyclestobeginnormaloperation. A LOW-to-HIGH transition on a FIFO Reset ( RST1,RST2)inputlatchesthe value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and Almost-Empty offset programming method. (For details see Table 1, Flag Programming,andtheProgrammingtheAlmost-EmptyandAlmost-FullFlags section). The relevant FIFO Reset timing diagram can be found in Figure 2. FIRST WORD FALL THROUGH ( FWFT) After Master Reset, the FWFT select function is active, permitting a choice between two possible timing modes: IDT Standard mode or First Word Fall Through (FWFT) mode. Once the Reset ( RST1,RST2)inputisHIGH,aHIGH on the FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode uses the Empty Flag function ( EFA, EFB) to indicate whether or not there are any words present in the FIFO memory. It uses the Full Flag function ( FFA, FFB) to indicate whether or not the FIFO memory has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using a formal read operation. Once the Reset ( RST1, RST2) input is HIGH, a LOW on the FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready function (ORA, ORB) to indicate whether or not there is valid data at the data outputs (A0-A35orB0-B35). ItalsousestheInputReadyfunction(IRA,IRB)toindicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to data outputs, no NOTES: 1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA. 2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB. 3. If parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation. FS1 FS0 RST1 RST2 X1 AND Y1 REGlSTERS(1) X2 AND Y2 REGlSTERS(2) HH ↑ X64 X HH X ↑ X64 HL ↑ X16 X HL X ↑ X16 LH ↑ X8 X LH X ↑ X8 LL ↑↑ Parallel programming via Port A(3) Parallel programming via Port A(3) TABLE 1 — FLAG PROGRAMMING |
Similar Part No. - IDT723672L12PQF |
|
Similar Description - IDT723672L12PQF |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |