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MPC5553MVM112R2 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc

Part # MPC5553MVM112R2
Description  Microcontroller
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5553MVM112R2 Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc

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MPC5553 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Overview
Freescale Semiconductor
2
PowerPC instruction set. This family of parts contains many new features coupled with high performance
CMOS technology to provide significant performance improvement over the MPC565.
The MPC5553 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the
8-kilobyte unified cache. The next level in the hierarchy contains the 64-kilobyte on-chip internal SRAM
and 1.5 Mbyte internal Flash memory. Both the internal SRAM and the Flash memory can hold
instructions and data. The external bus interface has been designed to support most of the standard
memories used with the MPC5xx family.
The complex I/O timer functions of the MPC5500 family are performed by an enhanced time processor
unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over
the TPU by providing 24-bit timers, double action hardware channels, variable number of parameters per
channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be
programmed using a high-level programming language.
The less complex timer functions of the MPC5500 family are performed by the enhanced modular
input/output system (eMIOS). The eMIOS’ 24 hardware channels are capable of single action, double
action, pulse width modulation (PWM), and modulus counter operation. Motor control capabilities include
edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPI), and enhanced serial communications
interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of
timer channels and general-purpose input/output (GPIO) signals.
The MCU of the MPC5553 has an on-chip 40-channel enhanced queued dual analog-to-digital converter
(eQADC).
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also found in the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing
of eQADC trigger sources, daisy chaining the DSPIs and external interrupt signal multiplexing.


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