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S71AL016D Datasheet(PDF) 7 Page - SPANSION |
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S71AL016D Datasheet(HTML) 7 Page - SPANSION |
7 / 76 page November 11, 2004 S71AL016D_02_04_00_A1 7 Pre l i m i n a r y Pin Description A16–A0 = 17 Address Inputs (Common) A19–A17 = 3 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE1#f = Chip Enable 1 (Flash) CE1#s = Chip Enable 1 (SRAM) CE2s = Chip Enable 2 (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output (Flash) UB# = Upper Byte Control (SRAM) LB# = Lower Byte Control (SRAM) RST#f = Hardware Reset Pin, Active Low (Flash) VCCf = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VCCs = pSRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally RFU = Reserved for Future Use Logic Symbol 20 16 DQ15–DQ0 A19–A0 CE# CE1#s OE# RST#f RY/BY# WE# LB# UB# CE2s |
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