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S71GL016A40BFW3J3 Datasheet(PDF) 6 Page - SPANSION |
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S71GL016A40BFW3J3 Datasheet(HTML) 6 Page - SPANSION |
6 / 9 page 4 S71GL016A Based MCPs S71GL016A_00_A1 June 20, 2006 Data Sheet ( A dv an ce I n f o r m a t i on) 4. Pin Description 5. Logic Symbol A19–A0 = 20 Address Inputs (Common and Flash only) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable 1 (pSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output (Flash 1) UB# = Upper Byte Control (pSRAM/SRAM) LB# = Lower Byte Control (pSRAM/SRAM) RESET# = Hardware Reset Pin, Active Low (Flash) WP#/ACC = Hardware Write Protect/Acceleration Pin (Flash) VCCf = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VCCs = pSRAM/SRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally 21 16 DQ15–DQ0 A20–A0 CE#f OE# WE# RESET# RY/BY# WP#/ACC UB# CE2s CE1#s LB# |
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