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S29NS032J Datasheet(PDF) 6 Page - SPANSION |
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S29NS032J Datasheet(HTML) 6 Page - SPANSION |
6 / 9 page 4S71NS-J S71NS-J_00_03 October 10, 2006 Data Sheet (Adv ance I nf or mation) 3. Input/Output Descriptions Signal Description Flash RAM R-UB# pSRAM Upper Byte Control X R-LB# pSRAM Lower Byte Control X A21–A16 Address Inputs XX ADQ15–ADQ0 Multiplexed Address/Data input/output X X R-CE# pSRAM Chip Select Input X F-CE# Flash Chip Enable Input. Asynchronous relative to CLK for the Burst mode. X OE# Output Enable Input. Asynchronous relative to CLK for the Burst mode. X X WE# Write Enable Input. XX VCC Device Power Supply (1.7 V–1.95 V). X X VSS Ground XX NC No Connect; not connected internally X X RDY Ready output; indicates the status of the Burst read. VOL= data invalid. WAIT# pin of pSRAM is shared with Flash RDY pin for synchronous pSRAM. XX CLK Clock input. The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. CLK is present on MuxpSRAM Type 3, but not on MuxpSRAM Type 2. As a result, it is a shared signal on S71NS064JA0, but a flash-only signal on S71NS032J. XX AVD# Address Valid input. Indicates to device that the valid address is present on the address inputs (address bits A15–A0 are multiplexed, address bits A22–A16 are address only). VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs XX F-RST# Hardware reset input. VIL= device resets and returns to reading array data X F-ACC At 12 V, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables program and erase functions. Should be at VIH for all other conditions. X R-CRE Command Register Enable of pSRAM X VCCQ I/O Power Supply (1.7 V to 1.95 V) X X VSSQ I/O Ground XX |
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