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S71WS512NA0BAWZZ3 Datasheet(PDF) 4 Page - SPANSION |
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S71WS512NA0BAWZZ3 Datasheet(HTML) 4 Page - SPANSION |
4 / 142 page 4 S71WS512NE0BFWZZ_00_A1 June 28, 2004 Advan ce In form ati o n Chip Erase Command Sequence ................................................................... 58 Sector Erase Command Sequence .................................................................59 Erase Suspend/Erase Resume Commands .................................................. 60 Figure 4. Erase Operation.................................................... 61 Program Suspend/Program Resume Commands ...................................... 61 Lock Register Command Set Definitions ................................................... 62 Password Protection Command Set Definitions ..................................... 62 Non-Volatile Sector Protection Command Set Definitions ..................63 Global Volatile Sector Protection Freeze Command Set ..................... 64 Volatile Sector Protection Command Set ...................................................65 SecSi Sector Entry Command .........................................................................65 Command Definition Summary ..................................................................... 66 Write Operation Status . . . . . . . . . . . . . . . . . . . . .69 DQ7: Data# Polling ........................................................................................... 69 Figure 5. Data# Polling Algorithm......................................... 70 RDY: Ready .......................................................................................................... 70 DQ6: Toggle Bit I ............................................................................................... 70 Figure 6. Toggle Bit Algorithm.............................................. 71 DQ2: Toggle Bit II ...............................................................................................72 Table 19. DQ6 and DQ2 Indications ..................................... 72 Reading Toggle Bits DQ6/DQ2 ......................................................................72 DQ5: Exceeded Timing Limits ........................................................................73 DQ3: Sector Erase Timer .................................................................................73 DQ1: Write to Buffer Abort ............................................................................73 Table 20. Write Operation Status ......................................... 74 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 75 Figure 7. Maximum Negative Overshoot Waveform................. 75 Figure 8. Maximum Positive Overshoot Waveform .................. 75 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 75 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .76 CMOS Compatible .............................................................................................76 Test Conditions ...................................................................................................77 Figure 9. Test Setup ........................................................... 77 Table 21. Test Specifications ............................................... 77 Switching Waveforms ........................................................................................77 Table 22. Key to Switching Waveforms ................................. 77 Figure 10. Input Waveforms and Measurement Levels............. 77 VCC Power-up ..................................................................................................... 78 Figure 11. VCC Power-up Diagram ........................................ 78 Pin Capacitance .................................................................................................. 78 AC Characteristics—Synchronous . . . . . . . . . . . 79 CLK Characterization ........................................................................................79 Figure 12. CLK Characterization ........................................... 79 Synchronous/Burst Read @ VIO = 1.8 V .....................................................80 Timing Diagrams .................................................................................................. 81 Figure 13. CLK Synchronous Burst Mode Read (rising active CLK). ....................................................................................... 81 Figure 14. Synchronous Burst Mode Read.............................. 82 Figure 15. Eight-word Linear Burst with Wrap Around ............. 82 Figure 16. Eight-word Linear Burst without Wrap Around......... 83 Figure 17. Linear Burst with RDY Set One Cycle Before Data.... 83 AC Characteristics—Asynchronous . . . . . . . . . . 84 Asynchronous Mode Read @ VIOpS = 1.8 V ............................................. 84 Timing Diagrams ................................................................................................. 84 Figure 18. Asynchronous Mode Read with Latched Addresses... 84 Figure 19. Asynchronous Mode Read..................................... 85 Hardware Reset (RESET#) .............................................................................. 85 Figure 20. Reset Timings..................................................... 85 Erase/Program Operations @ VIO = 1.8 V ................................................. 86 Figure 21. Asynchronous Program Operation Timings: WE# Latched Addresses ............................................................. 87 Figure 22. Synchronous Program Operation Timings: CLK Latched Addresses......................................................................... 88 Figure 23. Accelerated Unlock Bypass Programming Timing..... 88 Figure 24. Data# Polling Timings (During Embedded Algorithm) ... ........................................................................................ 89 Figure 25. Toggle Bit Timings (During Embedded Algorithm) ... 89 Figure 26. Synchronous Data Polling Timings/Toggle Bit Timings .. ........................................................................................ 90 Figure 27. DQ2 vs. DQ6 ..................................................... 90 Figure 28. Latency with Boundary Crossing when Frequency > 66 MHz................................................................................. 91 Figure 29. Latency with Boundary Crossing into Program/Erase Bank................................................................................ 91 Figure 30. Example of Wait States Insertion.......................... 92 Figure 31. Back-to-Back Read/Write Cycle Timings ................ 92 Erase and Programming Performance . . . . . . . . 93 128Mb pSRAM FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 FUNCTION TRUTH TABLE . . . . . . . . . . . . . . . 95 Asynchronous Operation (Page Mode) ..................................................... 95 FUNCTION TRUTH TABLE (Continued) . . . . 96 Synchronous Operation (Burst Mode) .......................................................96 STATE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . .97 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . 98 Power-up ...............................................................................................................98 Configuration Register ......................................................................................98 CR Set Sequence ................................................................................................98 FUNCTIONAL DESCRIPTION (Continued) . . 99 Address Key .........................................................................................................99 FUNCTIONAL DESCRIPTION (Continued) . 100 Power Down ...................................................................................................... 100 FUNCTIONAL DESCRIPTION (Continued) . . 101 Burst Read/Write Operation ..........................................................................101 FUNCTIONAL DESCRIPTION (Continued) . 102 CLK Input Function ..........................................................................................102 ADV# Input Function .......................................................................................102 WAIT# Output Function ................................................................................102 FUNCTIONAL DESCRIPTION (Continued) . . 103 Latency ..................................................................................................................103 FUNCTIONAL DESCRIPTION (Continued) . 104 Address Latch by ADV# .................................................................................104 Burst Length ........................................................................................................104 Single Write .........................................................................................................104 Write Control ....................................................................................................105 FUNCTIONAL DESCRIPTION (Continued) . 106 Burst Read Suspend ..........................................................................................106 Burst Write Suspend ........................................................................................106 FUNCTIONAL DESCRIPTION (Continued) . . 107 Burst Read Termination ..................................................................................107 Burst Write Termination ................................................................................107 ABSOLUTE MAXIMUM RATINGS (See WARNING below.) . . . . . . . . . . . . . . . . . . . . . . 108 RECOMMENDED OPERATING CONDITIONS (See WARNING below.) . . . . . . . . . . . . . . . . . . 108 (Referenced to VSS) ................................................................................... 108 DC CHARACTERISTICS . . . . . (Under Recommended Operating Conditions unless otherwise noted) . . . . . . . . Note *1,*2,*3 109 |
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