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S71NS128NB0BJWRT3 Datasheet(PDF) 7 Page - SPANSION |
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S71NS128NB0BJWRT3 Datasheet(HTML) 7 Page - SPANSION |
7 / 12 page October 10, 2006 S71NS-N_00_A3 S71NS-N MCP Products 5 Advance Information 4 Connection Diagrams/Physical Dimensions This section contains the I/O designations and package specifications for the S71NS-N. 4.1 Special Handling Instructions for FBGA Packages Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning meth- ods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. 4.2 Connection Diagrams 4.2.1 pSRAM Based Pinout, 56-Ball, VFBGA Notes: 1. Addresses are shared between Flash and RAM depending on the density of the pSRAM. 2. CLK and WAIT signals are Flash only for the S71NS064NA0-RT, while on that MCP, the CRE signal won't exist. Figure 4.1 pSRAM Based Pinout, 56-Ball, VFBGA MCP Flash-Only Addresses Shared Addresses Shared ADQ Pins S71NS128NC0 A22 A21-A16 ADQ15 – ADQ0 S71NS128NB0 A22-A21 A20-A16 ADQ15 – ADQ0 S71NS128NA0 A22-A20 A19-A16 ADQ15 – ADQ0 S71NS064NA0 A21-A20 A19-A16 ADQ15 – ADQ0 Flash/RAM Shared Only Flash Only Legend RAM Only No Connect (Distance between outer NC balls is 2x pitch) Reserved for Future Use K3 NC K14 NC A14 NC A1 NC D3 D6 D5 D7 D8 D9 D10 D4 E3 E6 E5 E7 E8 E9 E10 E4 E11 E12 F3 F6 F5 F7 F8 F9 F10 F4 F11 F12 G3 G6 G5 G7 G8 G9 G10 G4 G11 G12 H3 H4 H11 H12 C3 C7 C11 NC RFU R-LB# R-UB# RFU NC F-RDY/ R-WAIT A21 VSS CLK VCC F-ACC A19 D11 A17 A22 WE# VCCQ A16 A20 AVD# DNU F-RST# F-WP# A18 F-CE# VSSQ VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 NC RFU R-CE# R-CRE RFU NC C4 C8 C12 D12 H7 H8 56-ball Fine-Pitch Ball Grid Array pSRAM-Based Pinout (Top View, Balls Facing Down) |
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