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S71WS512PD0HFFLW0 Datasheet(PDF) 10 Page - SPANSION |
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S71WS512PD0HFFLW0 Datasheet(HTML) 10 Page - SPANSION |
10 / 15 page 8 S75WS-P based MCP/POP Products S75WS-P_00_02 September 6, 2006 Da ta Sh eet ( A dv an ce In f o r m at io n) N-CE# Input Chip Enable: The device enters a low-power Standby mode when the device is in Ready mode. The CE# signal is ignored when the device is in a Busy state (RY/BY# = L), such as during a Page Buffer Load or Erase operation, and will not enter Standby mode even if the CE# input goes high. The CE# signal may be inactive during the Page Buffer write and Page Buffer load of the array data. X N-WE# Input Write Enable: The WE# signal is used to control the acquisition of data from the I/O port. X N-RE# Output Read Enable: The RE# signal controls serial data output. Data is available tREA after the falling edge of RE#. The internal column address counter is also incremented (Address = Address + 1) on this falling edge. X N-WP# Input Write Protect: The WP# signal is used to protect the device from accidental programming or erasing. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. X Table 5.1 Input/Output Descriptions (Sheet 2 of 2) Symbol Signal Type Description WS (NOR) pSRAM MS (ORNAND) |
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