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UCD9080RHBT Datasheet(PDF) 6 Page - Texas Instruments |
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UCD9080RHBT Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 32 page  www.ti.com TIMING PARAMETERS FOR I2C INTERFACE VSS NC XIN NC RST MON1 MON2 MON3 EN2 EN1 SCL SDA NC MON5 MON4 NC 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 10 11 12 13 14 15 16 9 25 27 28 29 30 31 32 26 UCD9080 SLVS692A – SEPTEMBER 2006 – REVISED DECEMBER 2006 PARAMETER MIN MAX UNIT tof Output fall time from VOH to VOL(1) with a bus capacitance from 10 pF to 400 pF. 250(2) ns CI Capacitance for each pin. 10 pF fSCL SCL Clock Frequency 10 100 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU;STA Set-up time for repeated start condition 4.7 µs tSU;DAT Data set-up time 250 ns tr Rise time of both SDA and SCL signals 1000 ns tf Fall time of both SDA and SCL signals 300 ns tSU;STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs C(b) Capacitive load for each bus line 400 pF VnL Noise margin at the LOW level for each connected device (including hysteresis) 0.1 VDD V VnH Noise margin at the HIGH level for each connected device (including hysteresis) 0.2 VDD V (1) See the Electrical Characteristics section of this data sheet. (2) The maximum tf for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. RHB PACKAGE (TOP VIEW) 6 Submit Documentation Feedback |
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