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S72NS256ND0AJW720 Datasheet(PDF) 5 Page - SPANSION |
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S72NS256ND0AJW720 Datasheet(HTML) 5 Page - SPANSION |
5 / 17 page November 9, 2005 S72NS128_256ND0_00_B1 S72NS-N Based MCPs 3 Ad vance Information 1 MCP Block Diagrams Notes: 1. Amax indicates highest address bit for memory component: a. Amax = A23 for NS256N, A22 for NS128N b. Amax = A11 for 128 Mb DDR DRAM, A12 for 256-Mb DDR DRAM 2. For Flash, A0 – A15 is tied to DQ0 – DQ15. 3. For the NS512N, two NS-N devices are included. All signals are common to both except for CE#. F-CE# becomes F1-CE#, while the CE# for the second flash is F2-CE#. This way, the two NS-N devices are separately accessed. Figure 1.1. MCP Block Diagram MUX Flash Memory NS-N DDR DRAM Memory F-RST# F-VPP F-WP# F-CE# F-OE# F-WE# AVD# F-VSS RST# VPP WP# CE# OE# WE# AVD# VSS ADQ15-ADQ0 F-CLK F-RDY A16-Amax F-VCC F-VCCQ A15-A0 DQ15-DQ0 CLK RDY A16-Amax VCC VCCQ D-RAS# D-CAS# D-BA0 D-BA1 D-CKE D-WE# D-Amax - D-A0 D-VCC RAS# CAS# BA0 BA1 CKE WE# VCC D-VCCQ VCCQ CLK CLK# DQS0 DQS1 LDQM UDQM TEST DQ15-DQ0 VSS VSSQ D-CLK D-CLK# D-LDQS D-UDQS D-LDQM D-UDQM D-TEST D-DQ15 - D-DQ0 D-VSS D-VSSQ F2-CE# Second NS-N (if needed) (Note 3) |
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