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S75NS128NBGJWJZ3 Datasheet(PDF) 5 Page - SPANSION |
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S75NS128NBGJWJZ3 Datasheet(HTML) 5 Page - SPANSION |
5 / 10 page S75NS-N_00_01E May 3, 2006 S75NS-N 3 Da ta Shee t (Advance I nformation) 2. Input/Output Descriptions Table 2.1 identifies the input and output package connections provided on the device. Table 2.1 Input/Output Descriptions Symbol Signal Type Description NS (NOR) pSRAM MS (ORNAND) AMAX – A16 Input Address inputs X X ADQ15 – ADQ0 I/O Multiplexed Address/Data X X OE# Input Output Enable input. Asynchronous relative to CLK for the Burst mode. XX WE# Input Write Enable input. X X VSS Ground Ground X X F-RDY / R-WAIT Output Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY. XX CLK Input Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode XX AVD# Input Address Valid input. Indicates to device that the valid address is present on the address inputs. Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs XX F-RST# Input Hardware reset input. Low = device resets and returns to reading array data X F-WP# Input Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. X F-ACC Input Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. X F-CE# Input Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode. X VCC Power Flash 1.8 Volt-only single power supply X X R-CE1# Input Chip-enable input for pSRAM X R-CRE Input Control Register Enable (pSRAM) X R-VCC Power pSRAM Power Supply X R-UB# Input Upper Byte Control (pSRAM) X R-LB# Input Lower Byte Control (pSRAM) X N-CLE Input Command Latch Enable X N-ALE Input Address Latch Enable X N-CE# Input Chip Enable input for ORNAND X N-WE# Input Write Enable input X N-RE# Input Read Enable input X N-IO0 - N-IO7 I/O Data Input/Output X N-WP# Input Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. X N-RY/BY# Input Ready/Busy output X N-PRE Input Power-On Read Enable X N-VSS Ground Ground X N-VCC Power ORNAND 1.8 Volt-only single power supply. X DNU — Do Not Use NC — No Connect; not connected internally |
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