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S72NS128NE0AFW1K2 Datasheet(PDF) 11 Page - SPANSION |
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S72NS128NE0AFW1K2 Datasheet(HTML) 11 Page - SPANSION |
11 / 17 page November 9, 2005 S72NS128_256ND0_00_B1 S72NS-N Based MCPs 9 Ad vance Information 4 Ordering Information The order number (Valid Combination) is formed by the following: S72NS 256 N D0 AF W 7 K 0 PACKING TYPE 0= Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel MODEL NUMBER K = DRAM Type 1, 66 MHz Flash/133 MHz DRAM J = DRAM Type 1, 80 MHz Flash/133 MHz DRAM 3 = DRAM Type 5, 66 MHz Flash/133 MHz DRAM 2 = DRAM Type 5, 80 MHz Flash/133 MHz DRAM PACKAGE MODIFIER 7 = DDR DRAM, 133-ball, 11x10 mm, FBGA Multi-chip Package 1 = DDR DRAM, 133-ball, 8.0x8.0 mm, FBGA Multi-chip Package TEMPERATURE RANGE W = Wireless (-25 °C to +85°C) PACKAGE TYPE AF = Thin profile Fine-pitch BGA Pb-free package (0.5 mm pitch, 1.0 mm height) AJ = Thin profile Fine-pitch BGA Pb-free LF35 package (0.5 mm pitch, 1.0 mm height) ZJ = Thin profile Fine-pitch BGA Pb-free LF35 package (0.5 mm pitch, 1.2 mm height) DRAM AND DATA FLASH DENSITY D0 = 128 Mb DRAM, No Data Flash E0 = 256 Mb DRAM, No Data Flash PROCESS TECHNOLOGY N = 110 nm, MirrorBitTM Technology CODE FLASH DENSITY 512 = 512 Mb 256 = 256 Mb 128 = 128 Mb PRODUCT FAMILY S72NS Multi-Chip Product (MCP) 1.8 V Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus Valid Combinations Product Family Code Flash Density (Mb) Process Technology DRAM Density (Mb) Package Type/ Marking/ Material Temperature Range Package Modifier Model Number Packing Type S72NS 128 N D0 AF, AJ W 1 K, J, 2, 3 0, 2, 3 256 7 512 ZJ E0 Notes: 1. Packing Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations. |
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