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LT3463EDD Datasheet(PDF) 4 Page - Linear Integrated Systems |
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LT3463EDD Datasheet(HTML) 4 Page - Linear Integrated Systems |
4 / 8 page 4 LT3463/LT3463A 3463f BLOCK DIAGRA Figure 1. Block Diagram OPERATIO The LT3463 uses a constant off-time control scheme to provide high efficiency over a wide range of output cur- rent. Operation can be best understood by referring to the block diagram in Figure 1. When the voltage at the FB1 pin is slightly above 1.25V, comparator A1 disables most of the internal circuitry. Output current is then provided by capacitor C2, which slowly discharges until the voltage at the FB1 pin goes below the hysteresis point of A1 (typical hysteresis at the FB1 pin is 8mV). A1 then enables the internal circuitry, turns on power switch Q1, and the current in inductor L1 begins ramping up. Once the switch current reaches 250mA, comparator A2 resets the one- shot, which turns off Q1 for 300ns. Q1 turns on again and the inductor currents ramp back up to 250mA, then A2 again resets the one-shot. This switching action continues until the output voltage is charged up (until the FB1 pin reaches 1.25V), then A1 turns off the internal circuitry and the cycle repeats. The second switching regulator is an inverting converter (which generates a negative output) but the basic operation is the same. SHDN1 (Pin 9): Shutdown Pin for Switcher 1. Pull this pin above 1.5V to enable Switcher 1. Pull below 0.3V to turn it off. Do not leave this pin floating. FB1 (Pin 10): Feedback Pin for Switcher 1. Set the output voltage by selecting values for R1 and R2. GND (Pin 11): Exposed Pad. Solder this exposed pad directly to the local ground plane. This pad must be electrically connected for proper operation. PI FU CTIO S – + – + – + 3 300ns ONE-SHOT 25mV LT3463: RS1 = RS2 = 0.1Ω LT3463A: RS1 = 0.1Ω, RS2 = 0.063Ω 25mV 1.25V 1.25V A2 A1 Q1 10 VIN FB1 FB2 1 VOUT1 VOUT1 SW1 3463 F01 L1 VIN VIN R1 R2 VOUT1 VOUT2 VREF R4 R3 C1 C2 VOUT2 C3 – + 300ns ONE-SHOT A4 A3 Q2 11 8 4 7 6 5 SW2 GND D2 D2 D1 D3 SWITCHER 1 SWITCHER 2 L2 2 C4 SHDN2 SHDN2 9 SHDN1 SHDN1 RS1 RS2 |
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