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Preliminary Specification
This advanced data sheet contains product specifications which are subject to change without notice. Rev. 0.27
Integrated Memory Technologies, Inc.
2285 Martin Ave., STE A, Santa Clara, CA 95050. Tel. (408) 986-1088 Fax (408) 727-8696
IMT
b) Write Characteristics:
Parameter
Description
IM29LV001-55
IM29LV001-70
IM29LV001-90 IM29LV001-120
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tWC
Write command cycle time
55
70
90
120
ns
tAS
Address setup time
0
0
0
0
ns
tAH
Address hold time
35
45
55
60
ns
tDS
Data setup time
20
30
40
45
ns
tDH
Data hold time
0
0
0
0
ns
tOES
OE# setup time
0
0
0
0
ns
tOEH
OE# hold time
0
0
0
0
ns
tCS
CE# setup time
0
0
0
0
ns
tCH
CE# hold time
0
0
0
0
ns
tCP
CE# write pulse width
25
35
45
50
ns
tCPH
CE# write pulse width high
20
30
30
35
ns
tWS
WE# setup time
0
0
0
0
ns
tWH
WE# hold time
0
0
0
0
ns
tWP
WE# write pulse width
25
35
45
50
ns
tWPH
WE# write pulse width high
20
30
30
35
ns
tWHWH1
Byte programming time
30
30
30
30
µs
tWHWH2
Page erase time
9
9
9
9
ms
tWHWH3
Chip erase time
3
3
3
3
s
tCEP
CE# access time for Data#
Polling and Toggle bit read
55
70
90
120
ns
tOEP
OE# access time for Data#
Polling and Toggle bit read
25
35
45
60
ns
Test Conditions
Input rise and fall time ……………………………… 5 ns
Input pulse levels……………………………………. 0.0 V to 3.0 V
Timing measurement reference level
Input…………………………………………. 1.5 V
Output……………………………………….. 1.5 V
Output loading
55ns and 70 ns parts…………………….. 1 TTL load + 30 pF
90 ns and 120 ns parts…………………… 1 TTL load + 100 pF
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