ADM1191

Rev. 0 | Page 9 of 16

VOLTAGE AND CURRENT READBACK

The ADM1191 contains the components to allow voltage and

of the current sense amplifier and the voltage on the VCC pin

are fed into a 12-bit ADC via a multiplexer. The device can be

instructed to convert voltage and/or current at any time during

When all conversions are complete, the voltage and/or current

values can be read out to 12-bit accuracy in two or three bytes.

SERIAL BUS INTERFACE

Control of the ADM1191 is carried out via the serial system

fast mode (400 kHz maximum). The ADM1191 is connected to

this bus as a slave device, under the control of a master device.

The ADM1191 has a 7-bit serial bus slave address. When the

device powers up, it does so with a default serial bus address.

The three MSBs of the address are set to 010; the four LSBs are

determined by the state of the A0 pin and the A1 pin. There are

16 different configurations available on the A0 pin and A1 pin

(see Table 5). This scheme allows 16 ADM1191 devices to operate

A0 Configuration

A1 Configuration

Address

Low state

Low state

0x60

Low state

Resistor to GND

0x68

Low state

Floating

0x70

Low state

High state

0x78

Resistor to GND

Low state

0x62

Resistor to GND

Resistor to GND

0x6A

Resistor to GND

Floating

0x72

Resistor to GND

High state

0x7A

Floating

Low state

0x64

Floating

Resistor to GND

0x6C

Floating

Floating

0x74

Floating

High state

0x7C

High state

Low state

0x66

High state

Resistor to GND

0x6E

High state

Floating

0x76

High state

High state

0x7E

Figure 16 and Figure 17 show timing diagrams for general read

conditions for different types of read and write operations, which

1.

The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial

data line, SDA, while the serial clock line, SCL, remains

high. This indicates that a data stream follows. All slave

peripherals connected to the serial bus respond to the start

condition and shift in the next eight bits, consisting of a 7-

bit slave address (MSB first) plus an R/W bit that

determines the direction of the data transfer; that is,

whether data is written to or read from the slave device

(0 = write, 1 = read).

The peripheral whose address corresponds to the transmitted

address responds by pulling the data line low during the

low period before the ninth clock pulse, known as the

acknowledge bit, and holding it low during the high period

of this clock pulse. All other devices on the bus remain idle

while the selected device waits for data to be read from it

or written to it. If the R/W bit is 0, the master writes to the

slave device. If the R/W bit is 1, the master reads from the

slave device.

2.

Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit

from the slave device. Data transitions on the data line

must occur during the low period of the clock signal and

remain stable during the high period, because a low-to-

high transition when the clock is high can be interpreted as

a stop signal.

If the operation is a write operation, the first data byte after

the slave address is a command byte. This tells the slave

device what to expect next. It can be an instruction, such

as telling the slave device to expect a block write, or it can

be a register address that tells the slave where subsequent

data is to be written.

Because data can flow in only one direction, as defined by

the R/W bit, it is not possible to send a command to a slave

device during a read operation. Before doing a read

operation, it may first be necessary to do a write operation

to tell the slave what sort of read operation to expect and/or

the address from which data is to be read.

3.

When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls

the data line high during the 10th clock pulse to assert a

stop condition. In read mode, the master device releases the

SDA line during the low period before the ninth clock

pulse, but the slave device does not pull it low. This is

known as a no acknowledge. The master then takes the data

line low during the low period before the 10th clock pulse,

then high during the 10th clock pulse to assert a stop

condition.