Ultra-Low-Power, High-Dynamic-

Performance, 60Msps Analog Front End

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7

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Low Threshold

DD0–DD9, CLK, SCLK, DIN, CS

0.3 x

V

Input Leakage

DD0–DD9, CLK, SCLK, DIN, CS = OGND or

±5µA

Input Capacitance

5pF

DIGITAL OUTPUTS (DA0–DA7)

Output Voltage Low

0.2 x

V

Output Voltage High

0.8 x

V

Tri-State Leakage Current

±5µA

Tri-State Output Capacitance

5pF

guaranteed by design and characterization.

Note 2: The minimum clock frequency for the MAX5866 is 40MHz.

Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude

of the digital outputs. SINAD and THD are calculated using HD2 through HD6.

Note 4: Guaranteed by design and characterization.

Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec-

ond channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second

channel FFT test tone bins.

Note 6: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and

phase of the fundamental bin on the calculated FFT.

Typical Operating Characteristics

-110

-70

-90

-30

-50

-10

-80

-100

-40

-60

-20

0

05

10

15

20

25

30

ADC CHANNEL-IA FFT PLOT

FREQUENCY (MHz)

IA

QA

HD3

HD2

-110

-70

-90

-30

-50

-10

-80

-100

-40

-60

-20

0

ADC CHANNEL-QA FFT PLOT

FREQUENCY (MHz)

05

10

15

20

25

30

HD3

HD2

IA

QA

-110

-70

-90

-30

-50

-10

-80

-100

-40

-60

-20

0

ADC CHANNEL-IA TWO-TONE FFT PLOT

FREQUENCY (MHz)

05

10

15

20

25

30