Preliminary Data

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

June 2006

Rev 1

1/22

1

M36L0R7060U1 M36L0R7060L1

M36L0R7050U1 M36L0R7050L1

128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash

memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package

Feature summary

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Multi-Chip Package

– 1 die of 128 Mbit (8Mb x16, Mux I/O

Multiple Bank, Multi-level, Burst) Flash

Memory

– 1 die of 32 or 64Mbit Mux I/O, Burst

Pseudo SRAM

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Supply voltage

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Electronic signature

– Manufacturer Code: 20h

– Device Codes (Top Flash Configuration):

M36L0R7060U1: 882Eh,

M36L0R7050U1: 882Eh

– Device Codes (Bottom Flash Configuration)

M36L0R7060L1: 882Fh

M36L0R7050L1: 882Fh

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ECOPACK® package

Flash memory

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Multiplexed address/data

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Synchronous / asynchronous read

– Synchronous Burst Read mode: 66MHz

– Random Access: 85ns

■

Synchronous burst read suspend

programming time

– 10µs typical Word program time using

Buffer Enhanced Factory Program

command

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Memory organization

– Multiple Bank Memory Array: 8 Mbit Banks

– Parameter Blocks (Top or Bottom location)

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Security

– 64 bit unique device number

– 2112 bit user programmable OTP Cells

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100,000 program/erase cycles per block

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Dual operations

– program/erase in one Bank while read in

others

– No delay between Read and Write

operations

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Block locking

– All blocks locked at power-up

– Any combination of blocks can be locked

with zero latency

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Common Flash Interface (CFI)

PSRAM

■

Access time: 70ns

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Synchronous modes:

– Synchronous Write: continuous burst

– Synchronous Read: continuous burst or

fixed length: 4, 8 or 16 Words for 32 Mbit

devices or 4, 8,16 or 32 Words for 64 Mbit

devices

– Maximum Clock Frequency: 83MHz

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Low power consumption

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Low power features

– Partial Array Self-Refresh (PASR)

– Deep Power-Down (DPD) Mode

– Automatic Temperature-compensated Self-

Refresh

TFBGA88 (ZAM)

8 x 10mm

FBGA

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