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S30MS01GP25BAW510 Datasheet(PDF) 11 Page - SPANSION |
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S30MS01GP25BAW510 Datasheet(HTML) 11 Page - SPANSION |
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11 / 41 page  August 4, 2006 S30MS-P_00_A7 S30MS-P ORNANDTM Flash Family 9 Da ta Shee t (Prelim i nar y ) 4. Pin Names and Descriptions 4.1 Pin Names and Functions 4.2 Pin Descriptions The device is a byte/word serial access memory that utilizes time-sharing input of address information. The device pin-outs are configured as shown in 137-Ball MS01GP MCP-Compatible FBGA Pinout on page 5. Pin Name Pin Function I/O0 to I/O15 Data Input/Output CLE Command Latch Enable ALE Address Latch Enable CE#, CE1#, CE2# Chip Enable RE# Read Enable WE# Write Enable WP# Write Protect PRE Power on Read Enable RY/BY# Ready/Busy Output VCC Power VSS Ground N.C. No Connection Pin Description CLE Command Latch Enable: The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE# signal while CE# is low and CLE is High. ALE Address Latch Enable: The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE# if CE# is low and ALE is High. Input data is latched if CE# is low and ALE is Low. CE#, CE1#, CE2# Chip Enable: The device enters a low-power Standby mode when the device is in Ready mode. The CE# signal is ignored when the device is in a Busy state (RY/BY# = L), such as during a Page Buffer Load or Erase operation, and will not enter Standby mode even if the CE# input goes high. The CE# signal may be inactive during the Page Buffer write and Page Buffer load of the array data. The 2Gb device has two chip enable pins: CE1# and CE2# (one per die). WE# Write Enable: The WE# signal is used to control the acquisition of data from the I/O port. RE# Read Enable: The RE# signal controls serial data output. Data is available tREA after the falling edge of RE#. The internal column address counter is also incremented (Address = Address + 1) on this falling edge. I/O0 to I/O7 I/O Port: The I/O0 to I/O7 pins are used as a port for transferring address, command, and input/output data to and from the device. I/O8 to I/O15 I/O Port: The I/O8 to I/O15 pins are used as a port for transferring input/output data to and from the device in x16 mode only. I/O8 to I/O15 pins must be low level during address and command input. WP# Write Protect: The WP# signal is used to protect the device from accidental programming or erasing. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. RY/BY# Ready/Busy:The RY/BY# output signal is used to indicate the operating condition of the device. The RY/BY# signal is in Busy state (RY/BY# = L) during the Program, Erase, and Read operations and return to Ready state (RY/BY# = H) after completion of the operation. The output buffer for this signal is an open drain. PRE Power-on Read Enable: The PRE controls auto read operation executed during power-on. The power-on auto- read is enabled when PRE pin in tied to VCC. VSS Ground: VSS is the Ground. N.C No Connection: Lead is not internally connected. |
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