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MN3307 Datasheet(PDF) 1 Page - Panasonic Semiconductor |
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MN3307 Datasheet(HTML) 1 Page - Panasonic Semiconductor |
1 / 5 page MN3300 Series 1 MN3307 1024-Stage Ultra Low Voltage Operation BBD for Audio Signals s Overview The MN3307 is a 1024-stage ultra low voltage operation BBD variable delay line in audio frequency range. The device operates on +3 V supply and provides a signal delay up to 51.2 ms and is suitable for use as reverberation effect of low voltage operation audio equip- ment such as portable stereo, radio cassette recorder and microphone. s Features • Variable signal delay of the audio signal : 1.024 to 51.2 ms • Wide range of supply voltage : 1.8 to 5.0 V • No insertion loss : L i=0 dB typ. • Wide dynamic range : S/N=69 dB typ. • Low distortion : THD=0.6 % typ. (V i=0.22 Vrms) • Clock frequency range : 10 to 200 kHz (1.8 V≤V DD<4.0 V) 10 to 500 kHz (4.0 V ≤V DD≤5.0 V) • N-channel 2-layer silicon gate process • 8-Pin Dual-In-Line Plastic Package s Applications • Reverberation and echo effects of audio equipment such as radio cassette recorder, car radio, portable radio, portable stereo, echo microphone and Karaoke machine, etc. • Sound effect of electronic musical instruments • Variable or fixed delay of analog signals DIP008-P-0300 Pin No. Symbol Pin Name Description 1 GND Ground pin Connected to ground. 2 CP2 Clock input 2 Basic clock pulse is applied to transfer electric charge of BBD. 3 IN Signal input pin Analog signal to be delayed is input. Most suitable DC bias should be applied to this pin. 4VDD VDD apply pin Bias is applied to the gate of MOS transistor which is inserted in series with clock pulse input gate of the BBD transfer gate. Furthermore, voltage is supplied to step-up circuit. 5VD1 VD1 apply pin The same phase clock pulse as CP1 is applied through capacitor. 6 CP1 Clock input 1 Clock pulse of inverted phase to CP2 is applied. 7 OUT Output pin Composed signal of 1024th and 1025th stages is output. 8VD2 VD2 apply pin The same phase clock pulse as CP2 is applied through capacitor. s Pin Descriptions s Pin Assignment 1024-Stage BBD 8 7 IN 3 VD2 OUT VD1 5 s Block Diagram 1 2 MN3307 3 4 VD2 OUT CP1 VD1 GND CP2 IN VDD 8 7 6 5 |
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