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FX-428-DFC-A3P2B Datasheet(PDF) 3 Page - Vectron International, Inc |
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FX-428-DFC-A3P2B Datasheet(HTML) 3 Page - Vectron International, Inc |
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3 / 8 page  FX-427 Low Jitter Frequency Translator Vectron International, 267 Lowell Road, Hudson, NH 03051 Tel: 1-88-VECTRON-1 • Web: www.vectron.com Page 3 of 8 Rev: 8Nov06 Figure 4. Pin Configuration Table 2. Pin Out Pin # Symbol I/O Level Function 1 SEL0 I LVCMOS Frequency Select - see table 3 2 SEL1 I LVCOMS Frequency Select – see table 3 3 GND GND Supply Case and Electrical Ground 4 Not present 5 VMON O Analog (0 – Vcc) VCXO Control Voltage Monitor Under locked conditions VMON should be > 0.3V and <3.0V. The input frequency may be out of range if the voltage exceeds these levels. 6 OD I LVCMOS Output Disable Disabled = Logic “1” Enabled = Logic “0” or no connect 7 LD O LVCMOS Lock Detect Locked = Logic “1” Loss of Lock = Logic “0” 8 FOUT1 O LCPECL Frequency Output – Primary 9 CFOUT1 O LVPECL Complimentary Frequency Output - Primary 10 FOUT2 O LVPECL Divided-Down VCSO/VCXO Output, or Disabled 11 CFOUT2 O LVPECL Complimentary Divided-Down VCSO/VCXO Output, or Disabled 12 GND GND Supply Case and Electrical Ground 13 FIN I LVCMOS or LVPECL Input Frequency – AC Coupled 14 VCC VCC Supply Power Supply Voltage (3.3 V ±5%) Table 3. Control Logic (LVCMOS) SEL0 SEL1 CLOCK INPUT 0 0 FIN1 0 1 FIN2 1 0 FIN3 1 1 FIN4 |
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