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Rev.01
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64Mb SDRAM
Raed data is available after /CAS latency requirements
have been met. This command sets the burst start
address given by the column.
( Figure. 5 Column address and read command
)
Read command ( /CS, /CAS = Low , / RAS, /WE = High )
Add
/CS
CLK
/RAS
/CAS
/WE
BA
A10
CKE
‘ H ’
This command is a request to begin the CBR refresh
operation. The refresh address is generated internally.
Before
Executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (Precharged )
state and ready for a row activate command. During tRC
period ( from refresh command to refresh or activate
command ), the EM482M3244VTA cannot accept any
other command.
( Figure. 6 Auto refresh command
)
Auto refresh command ( /CS, /RAS, /CAS = Low, /WE, CKE = High )
Add
/CS
CLK
/RAS
/CAS
/WE
BA
A10
CKE
‘ H ’
Column