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S29WS128P0PBFW003 Datasheet(PDF) 3 Page - SPANSION |
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S29WS128P0PBFW003 Datasheet(HTML) 3 Page - SPANSION |
3 / 89 page This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. Publication Number S29WS-P_00 Revision A Amendment 7 Issue Date November 8, 2006 Features Single 1.8 V read/program/erase (1.70–1.95 V) 90 nm MirrorBit™ Technology Simultaneous Read/Write operation with zero latency Random page read access mode of 8 words with 20 ns intra page access time Full /Half drive output slew rate control 32 Word / 64 Byte Write Buffer Sixteen-bank architecture consisting of 32/16/8 Mwords for 512/256/128P, respectively Four 16 Kword sectors at both top and bottom of memory array 510/254/126 64Kword sectors (WS512/256/128P) Programmable linear (8/16/32) with or without wrap around and continuous burst read modes Secured Silicon Sector region consisting of 128 words each for factory and 128 words for customer 20-year data retention (typical) Cycling Endurance: 100,000 cycles per sector (typical) Command set compatible with JEDEC (42.4) standard Hardware (WP#) protection of top and bottom sectors Dual boot sector configuration (top and bottom) Handshaking by monitoring RDY Offered Packages – WS512P/WS256P/WS128P: 84-ball FBGA (11.6 mm x 8 mm) Low VCC write inhibit Persistent and Password methods of Advanced Sector Protection Write operation status bits indicate program and erase operation completion Suspend and Resume commands for Program and Erase operations Unlock Bypass program command to reduce programming time Synchronous or Asynchronous program operation, independent of burst control register settings ACC input pin to reduce factory programming time Support for Common Flash Interface (CFI) General Description The Spansion S29WS512/256/128P are Mirrorbit TM Flash products fabricated on 90 nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate data and address pins. These products can operate up to 108 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered power consumption. Performance Characteristics S29WS-P MirrorBit ™ Flash Family S29WS512P, S29WS256P, S29WS128P 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory Data Sheet (Advance Information) Read Access Times Speed Option (MHz) 108 Max. Synch Access Time (tIACC)80 Max. Synch. Burst Access, ns (tBACC)7.6 Max. Asynch. Access Time, ns (tACC)80 Max OE# Access Time, ns (tOE)7.6 Current Consumption (typical values) Continuous Burst Read @ 108 MHz 36 mA Simultaneous Operation 108 MHz 40 mA Program 20 mA Standby Mode 20 µA Typical Program & Erase Times Single Word Programming 40 µs Effective Write Buffer Programming (VCC) Per Word 9.4 µs Effective Write Buffer Programming (VACC) Per Word 6 µs Sector Erase (16 Kword Sector) 350 ms Sector Erase (64 Kword Sector) 600 ms |
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