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BIAS CURRENT GENERATION AND APC LOOP

ANALOG REFERENCE

POWER-ON RESET AND REGISTER LOADING SEQUENCE

ONET1191V

SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006

Table 6. Register Functionality (continued)

SYMBOL

REGISTER

FUNCTION

EQADJ2

Equalizer adjustment bit 2

EQENB = 0

EQADJ1

Equalizer adjustment bit 1

Maximum equalization for 0000 0000

EQADJ0

Equalizer adjustment bit 0 (LSB)

Minimum equalization for 1111 1111

The bias current generation and APC loop are controlled by means of the two-wire interface. In open-loop

operation, selected by setting OLE = 1 (bit 4 of register 0), the bias current is set directly by the 8-bit-wide

control word BIASC[0..7] (register 2). In automatic power control mode, selected by setting OLE = 0, the bias

current depends on the register settings BIASC[0..7] and the coupling ratio (CR) between the VCSEL bias

Two photodiode current ranges can be selected by means of the PDR register (bit 5 of register 0). The

photodiode range should be chosen to keep the laser bias control DAC close to the center of its range. This

keeps the laser bias current setpoint resolution high and the loop settling time constant within specification.

For details regarding the bias current setting in open- as well as in closed-loop mode, see Table 6.

In closed-loop mode, the photodiode polarity bit, PDP, must be set for common-anode or common-cathode

configuration to ensure proper operation. In open-loop mode, if a photodiode is present, the photodiode polarity

bit must be set to the opposite setting.

The ONET1191V VCSEL driver is supplied by a single 3.3-V

±10% supply voltage connected to the VCC pins.

This voltage is referred to ground (GND).

On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which

all other internally required voltages and bias currents are derived.

An external zero-temperature-coefficient resistor must be connected from the RZTC pin of the device to ground

(GND). This resistor is used to generate a precise, zero-TC current, which is required as a reference current for

the on-chip DACs.

In order to minimize the module component count, the ONET1191V provides an on-chip temperature sensor.

The output voltage of the temperature sensor is available at the TS pin.

Note that the voltage at TS is not buffered. As a result, TS can only drive capacitive loads.

The ONET1191V has power-on-reset circuitry, which ensures that all registers are reset to zero during startup.

registers are loaded in the following order:

1. Bias current register (register 2, 010b)

2. Modulation current register (register 1, 001b)

3. Control register (register 0, 000b)

4. Loading of equalizer register (register 3, 011b) is not required.

enable bit ENA is set to 1 and the disable pin DIS is low.

The ONET1191V can be disabled using either the ENA control register bit or the disable pin DIS. In both cases,

the internal registers are not reset. After the disable pin DIS is set low and/or the enable bit ENA is set back

to 1, the part returns to its prior output settings.

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