EM25LV512

512 K (64K x 8) Bits Serial Flash Memory

SPECIFICATION

Status Register

The Status Register contains a number of status and control bits that can be read or set by

specific instructions. Refer to Table 3 below for details.

BUSY Bit

The (BUSY) bit is a read only bit in the status register, which is set to “1” state when the device

is executing the Write Status Register, Program, or Erase cycle while the device ignores

further instructions except for the Read Status Register instruction. When the Program,

Erase, or Write Status Register instruction is completed, the (BUSY) bit will be cleared to “0”

state indicating the device is ready for further instructions.

WEL Bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When setting to “1,” the internal Write Enable Latch is set. When setting to “0,” the internal

Write Enable Latch is reset and no Write Status Register, Program, nor Erase instruction is

accepted.

BP1, BP0 Bits

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Program and Erase instructions. These bits are written with the

Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0)

bits is set to “1”, the relevant memory area, as defined in Table 4, becomes protected against

Page Program (PP) and Block Erase (BE) instructions. The Block Protect (BP1, BP0) bits can

be written provided that the Hardware Protected mode has not been set. The Chip Erase

(CE) instruction is executed if, and only if, both Block Protect (BP1, BP0) bits are set to “0.”

SRWD Bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W#) signal. The Status Register Write Disable bit and Write Protect signal allow the

device to be located in the Hardware Protected mode (when the Status Register Write Disable

(SRWD) bit is set to “1,” and Write Protect (W#) is driven Low). In this mode, the non-volatile

bits of the Status Register (SRWD, BP1, and BP0) become read-only bits and the Write Status

Register (WRSR) instruction is no longer accepted for execution.

This specification is subject to change without further notice. (11.08.2004 V1.0)

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