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HLX6256REN Datasheet(PDF) 6 Page - Honeywell Solid State Electronics Center |
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HLX6256REN Datasheet(HTML) 6 Page - Honeywell Solid State Electronics Center |
6 / 12 page HLX6256 6 HIGH IMPEDANCE NCS NOE DATA VALID CE TAVAVR TAVQV TAXQX TSLQV TSLQX TSHQZ TEHQX TEHQV TGLQX TGLQV TGHQZ TELQZ ADDRESS (NWE = high) DATA OUT TAVAVR Address Read Cycle Time 25 ns TAVQV Address Access Time 25 ns TAXQX Address Change to Output Invalid Time 3 ns TSLQV Chip Select Access Time 25 ns TSLQX Chip Select Output Enable Time 5 ns TSHQZ Chip Select Output Disable Time 14 ns TEHQV Chip Enable Access Time (4) 25 ns TEHQX Chip Enable Output Enable Time (4) 5 ns TELQZ Chip Enable Output Disable Time (4) 14 ns TGLQV Output Enable Access Time 9 ns TGLQX Output Enable Output Enable Time 0 ns TGHQZ Output Enable Output Disable Time 12.6 ns READ CYCLE AC TIMING CHARACTERISTICS (1) Worst Case (3) Symbol Parameter Typical -55 to 125 °C Units (2) Min Max (1) Test conditions: input switching levels,VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading C L>50 pF, or equivalent capacitive output loading CL=5 pF for TSHQZ, TELQZ TGHQZ. For C L >50 pF, derate access times by 0.02 ns/pF (typical). (2) Typical operating conditions: VDD=3.3 V, TA=25 °C, pre-radiation. (3) Worst case operating conditions: VDD=3.0 V to 3.6 V, post total dose at 25 °C. (4) Chip Enable (CE) pin not available on 28-lead FP or DIP. |
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