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CY7C4282V
CY7C4292V
10
Notes:
23. Clocks are free-running in this case.
24. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
25. For the synchronous PAE and PAF flags an appropriate clock cycle is necessary after tRTR to update these flags.
Switching Waveforms (continued)
Write Programmable Registers
WCLK
tCLKH
tCLKL
PAE OFFSET
LSB
D0 –D8
WEN
tENS
PAF OFFSET
MSB
tCLK
tDS
tDH
4282V–14
PAE OFFSET
MSB
PAF OFFSET
LSB
tENH
LD
tENS
PAF OFFSET
MSB
PAF OFFSET
LSB
tENH
Read Programmable Registers
RCLK
tCLKH
tENS
tCLKL
PAE OFFSET LSB
Q0 –Q15
REN
tENS
PAE OFFSET MSB
tCLK
UNKNOWN
tA
4282V–15
LD
Retransmit Timing
REN/WEN
FL/RT
tPRT
tRTR
4282V–16
EF/FF
[23, 24, 25]