IS61SF25616-12B datasheet(9/16 Pages) ISSI

Part #	IS61SF25616-12B

Description	256K x 16, 256K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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IS61SF25616

IS61SF25618

ISSI®

Integrated Silicon Solution, Inc. — 1-800-379-4774

9

Rev. A

04/17/01

READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

8

8.5

10

12

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

fMAX(3)

Clock Frequency

—

100

—

90

—

66

—

66

MHz

tKC(3)

Cycle Time

10

—

11

—

15

—

15

—

ns

tKH

Clock High Time

4

—

4.5

—

4.5

—

4.5

—

ns

tKL(3)

Clock Low Time

4

—

4.5

—

4.5

—

4.5

—

ns

tKQ(3)

Clock Access Time

—

8

—

8.5

—

10

—

12

ns

tKQX(1)

Clock High to Output Invalid

2

—

2

—

2

—

2

—

ns

tKQLZ(1,2)

Clock High to Output Low-Z

0

—

0

—

0

—

0

—

ns

tKQHZ(1,2)

Clock High to Output High-Z

2

3.5

2

3.5

2

3.5

2

3.5

ns

tOEQ(3)

Output Enable to Output Valid

—

3.5

—

3.5

—

3.5

—

5ns

tOELZ(1,2)

Output Enable to Output Low-Z

0

—

0

—

0

—

0

—

ns

tOEHZ(1,2)

Output Disable to Output High-Z

—

3.5

—

3.5

—

3.5

—

3.5

ns

tAS(3)

Address Setup Time

2

—

2

—

2

—

4

—

ns

tSS(3)

Address Status Setup Time

2

—

2

—

2

—

4

—

ns

tWS(3)

Write Setup Time

2

—

2

—

2

—

4

—

ns

tCES(3)

Chip Enable Setup Time

2

—

2

—

2

—

4

—

ns

tAVS(3)

Address Advance Setup Time

2

—

2

—

2

—

4

—

ns

tAH(3)

Address Hold Time

0.5

—

0.5

—

0.5

—

1.5

—

ns

tSH(3)

Address Status Hold Time

0.5

—

0.5

—

0.5

—

1.5

—

ns

tWH(3)

Write Hold Time

0.5

—

0.5

—

0.5

—

1.5

—

ns

tCEH(3)

Chip Enable Hold Time

0.5

—

0.5

—

0.5

—

1.5

—

ns

tAVH(3)

Address Advance Hold Time

0.5

—

0.5

—

0.5

—

1.5

—

ns

Notes:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.

2. Tested with load in Figure 2.

3. Tested with load in Figure 1.

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