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SN74SSTE32882 Datasheet(PDF) 2 Page - Texas Instruments

Part # SN74SSTE32882
Description  28-Bit to 56-Bit Registered Buffer With Address Parity Test and One Pair to Four Pair Differential Clock PLL Driver
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74SSTE32882 Datasheet(HTML) 2 Page - Texas Instruments

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QA A13
QA A8
RSVD
GND
RESET
RSVD
QERR
GND
RSVD
QB A8
QB A13
QA A14
QA A7
QB A7
QB A14
QA A9
QA A6
V DD
V DD
V DD
V DD
V DD
QB A6
QB A9
QA A11
QA A5
GND
GND
GND
GND
GND
QB A5
QBA11
QA A2
QA A4
V DD
V DD
V DD
V DD
V DD
QB A4
QB A2
QA A1
QA A3
GND
GND
GND
GND
GND
QB A3
QB A1
QA A0
QA BA1
V DD
V DD
V DD
V DD
V DD
QB BA1
QB A0
QA A12
QA BA0
GND
GND
GND
GND
GND
QB BA0
QB A12
QA BA2
QACS1
V DD
V DD
V DD
V DD
V DD
QBCS1
QB BA2
QA A15
QACKE0
GND
GND
GND
GND
GND
QBCKE0
QB A15
QA WE
QA CS0
V DD
V DD
V DD
V DD
V DD
QBCS0
QB WE
QA A10
QACKE1
GND
GND
GND
GND
GND
QBCKE1
QB A10
QA CAS
QAODT0
V DD
V DD
V DD
V DD
V DD
QB ODT0
QB CAS
QA RAS
QAODT1
D8 (A3)
GND
GND
GND
D A4
QB ODT1
QB RAS
DCKE1
D A14
D9 (A 15)
D A5
RSVD
D A2
D A1
D A10
DODT1
DCKE0
DCS0
DCS1
DODT 0
D A12
D BA2
Y 1
PV SS
V DD
PV DD
Y 0
D A13
D CAS
D A9
D A11
Y 1
PV SS
GND
PV DD
Y 0
D RAS
D WE )
D A8
D A6
FBIN
Y 3
AV SS
CK
RSVD
Y 2
FBOUT
D A0
D BA0
D A7
RSVD
FBIN
Y 3
AV DD
CK
V REF
Y 2
FBOUT
PAR_IN
D BA1
A
B
C
D
E
F
H
G
J
K
L
M
N
P
R
T
U
V
W
Y
2
1
3
4
5
6
7
8
9
10
11
W
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
Y
SN74SSTE32882
SCAS840 – NOVEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ZAL PACKAGE
TERMINAL ASSIGNMENT FOR DEVICE
(TOP VIEW)
(1)
Each pin name in parentheses indicates
the DDR3 DIMM signal name.
(2)
Balls A3, A9, R6, W7 and Y2 are reserved
for future functions, and must not be
connected on the system. However, a ball
on the device and connecting pad on the
module are required in those locations.
(3)
Ball A6 is reserved for future function. The
device needs to tolerate floating on this
pin.
TERMINAL FUNCTIONS
TERMINAL NAME
DESCRIPTION
ELECTRICAL TYPE
AVSS
Analog ground (PLL)
Analog ground input
AVDD
Analog power (PLL)
1.5 V nominal
PVSS
Logic and output ground (PLL)
Ground input
PVDD
Logic and output power (PLL)
1.5 V nominal
GND
Ground (register)
Ground input
VDD
Power supply voltage (register)
1.5 V nominal
VREF
Input reference voltage
VDD/2 (0.75 V) nominal
Positive master clock input with a (10 k
Ω to 100 kΩ) pull-down resistor
Differential input
CK
Complementary master clock input with a (10 k
Ω to 100 kΩ) pull-down resistor
Differential input
Positive feedback clock input with a (10 k
Ω to 100 kΩ) pull-down resistor
Differential input
FBIN
Complementary feedback clock input with a (10 k
Ω to 100 kΩ) pull-down resistor
Differential input
Asynchronous reset input – Resets registers and disables VREF, data and clock
RESET
differential-input receivers. When RESET is low, all the Q outputs are inactive with
LVCMOS input
QCKEx being forced low and the QERR outputs are forced high.
2
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