AN1504/D

http://onsemi.com

3

Figure 4. Metastable Flip−Flop Output Response

28.6300 NS

31.1300 NS

33.6300 NS

CH. 3 = 150.0 mV/DIV

START = 30.8500 NS

TIMEBASE = 500 PS/DIV

DELTA T = 710.0 PS

STOP = 31.5600 NS

The flip−flop shown in Figure 5 can be divided into two

functional blocks: Master latch and Slave latch. Under

optimal operating conditions the clock is low when data

arrives at the input to the master latch; after the specified

set−up time the clock input is raised to a high level, and the

data is latched. When the clock signal goes to the low state,

the slave portion of the circuit becomes transparent and

transfers the latched data to the output. Changes at the input

will have no affect on the output when the “slave latch” is

transparent.

The master and slave latches each consist of two

subsections: Data and Regenerative (Figure 5). Since the

master latch accepts signals from external sources it is the

section most susceptible to metastability problems. When

the clock signal goes to a high state the current in the master

latch clock differential pair switches from the regenerative

to the data side. If the set−up and hold times are observed the

circuit will function properly. However, if the data and clock

signals change such that the set−up and hold times are

violated, the data differential pair, the regenerative

differential pair and the clock differential pair for the master

will share the same switch current. In addition there will not

be enough current to charge and discharge the transistor

parasitic capacitances, creating an RC feedback loop via the

collector nodes of the data and regenerative differential

pairs. Thus the master latch enters a metastable state which

appears at the output since the slave latch is transparent

under these conditions. Theoretically, there is no upper

bound on the length of time this metastable state can last,

although in practice circuits eventually do leave the

metastable region.

RESET

SET

SLAVE

LATCH

MASTER LATCH

REGENERATIVE

DATA

REGENERATIVE

DATA

CLOCK

DATA

DATA

CLOCK

Figure 5. ECLinPS D Flip−Flop