Philips Semiconductors

Product data

HSTL16918

9-bit to 18-bit HSTL-to-LVTTL memory address latch

2

2001 Jun 16

853-2258 26484

FEATURES

Level III specifications

Protection exceeds 2000 V to HBM per method A114.

exceeds 100 mA.

(TSSOP48)

DESCRIPTION

The HSTL16918 is a 9-bit to 18-bit D-type latch designed for

the Q outputs provide LVTTL levels.

The HSTL16918 is particularly suitable for driving an address bus to

two banks of memory. Each bank of nine outputs is controlled with

its own latch-enable (LE) input.

Each of the nine D inputs is tied to the inputs of two D-type latches

that provide true data (Q) at the outputs. While LE is LOW the Q

outputs of the corresponding nine latches follow the D inputs. When

LE is taken HIGH, the Q outputs are latched at the levels set up at

the D inputs.

The HSTL16918 is characterized for operation from 0 to +70

°C.

PIN CONFIGURATION

SW00768

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

2Q1

1Q1

GND

D1

D2

D3

GND

1LE

GND

GND

2LE

GND

D4

D5

D6

D7

D8

GND

2Q7

1Q7

2Q6

1Q6

GND

2Q5

1Q5

GND

2Q4

1Q4

2Q3

1Q3

GND

2Q2

1Q2

21

22

23

24

25

26

27

28

D9

GND

2Q9

1Q9

2Q8

1Q8

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

DWG NUMBER

48-pin plastic thin shrink small outline package

(TSSOP48)

0 to +70

°C

HSTL16918DGG

SOT362-1