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XRT4000 Datasheet(PDF) 6 Page - Exar Corporation |
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XRT4000 Datasheet(HTML) 6 Page - Exar Corporation |
6 / 46 page XRT4000 Rev. 1.00 - 6 - PIN DESCRIPTION Pin # Symbol DTE Mode DCE Mode Type Function 1VDD Digital VDD for Receiver 1 - Connect to +5V 2GND Digital GND for Receiver 1 3M0 I Mode Control - Mode Select Input 0; Internal 20K Ω pull-up 4M1 I Mode Control - Mode Select Input 1; Internal 20K Ω pull-up 5M2 I Mode Control - Mode Select Input 2; Internal 20K Ω pull-up 6 EN_FLTR I Enable Glitch Filter on Receiver 4, 5, 6, 7, 8 inputs. Internal 20K Ω pull-down 7 EN_TERM I Enable input termination for Receiver 1, 2, 3 in V.11 Mode. Internal 20K Ω pull-down 8 LATCH* I Mode Control Input Latch Enable - Logic 0: Changes on M0, 1, 2, EN_FLTR, and EN_TERM pins cause mode changes (input latches in transparent state). Logic 1: Changes on these input pins do not cause mode changes (input latches in latched state). Internal 20K Ω pull- down 9 VSS Digital VSS for Transmitter 4, 5, 6. Connect to -6V 10 VSS Analog VSS for bias generation Connect to -6V 11 GND Digital GND for Transmitter 7, 8 12 CLKFS O Internal Clock Generated - 500kHz 13 TX4D D_RTS D_CTS I Transmitter 4 - Digital Data Input from equipment 14 VDD Digital VDD for Transmitter 4, 5, 6; Connect to +5V 15 TX4B RTSB CTSB O Transmitter 4 - Positive Data Differential Output to line 16 TX4A RTSA CTSA O Transmitter 4 - Negative Data Differential Output to line 17 TX5A DTRA DSRA O Transmitter 5 - Negative Data Differential Output to line 18 TX5B DTRB DSRB O Transmitter 5 - Positive Data Differential Output to line 19 GND Digital GND for Transmitter 4, 5, 6 20 TX5D D_DTR D_DSR I Transmitter 5 - Digital Data Input from equipment 21 TX8D D_RL D_RI I Transmitter 8 - Digital Data Input from equipment 22 LP* I Loopback Enable - Active low; Logic 0: Loopback enabled. Logic 1: Loopback disabled. Internal 20K Ω pull-up 23 TX8O RLA RIA O Transmitter 8 - Single Ended Data Output to line 24 VSS Digital VSS for Transmitter 7, 8; Connect to -6V 25 VDD Digital VDD for Transmitter 7, 8; Connect to +5V 26 EN_OUT* I Output Enable for Receiver 5, 8; Internal 20K Ω pull-down 27 REG I Register Control - Logic 1: TX5D, TX8D signal values will be latched on the positive edge of REG_CLK, Logic 0: The Register flip-flop is bypassed therefore REG_CLK has no effect on these signals. Internal 20K Ω pull-down 28 VSS Analog VSS for Receiver 4, 5, 6; Connect to -6V 29 VDD Analog VDD for Receiver 4, 5, 6; Connect to +5V 30 VDD Analog VDD for Receiver 7, 8; Connect to +5V 31 RX8D D_RI D_RL O Receiver 8 - Digital Data Output to equipment 32 GND Analog GND for Receiver 7, 8 33 RX8I RIA RLA I Receiver 8 - Single Ended Data Input from line 34 VSS Analog VSS for Receiver 7, 8; Connect to -6V Note: An asterisk (*) following a pin symbol indicates that the pin is active low. Names begining with D_ are digital signals. Names ending with B and A are the positive and negative polarities of differential signals respectively. |
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Similar Description - XRT4000 |
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