7 / 8 page
PDM41028
Rev. 2.2 - 4/29/98
7
1
2
3
4
5
6
7
8
9
10
11
12
AC Electrical Characteristics
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table
Low VCC Data Retention Waveform
Data Retention Electrical Characteristics (LA Version Only)
NOTES: (For three previous Electrical Characteristics tables)
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured
±200 mV from steady state voltage.
2. At any given temperature and voltage condition, tHZCE is less than tLZCE.
3. This parameter is sampled.
4. WE is high for a READ cycle.
5. The device is continuously selected. Chip Enable is held in its active state.
6. The address is valid prior to or coincident with the latest occuring Chip Enable.
7. Vcc = 5V
± 5%.
Description
-10(7)
-12(7)
-15
WRITE Cycle
Sym
Min.
Max.
Min.
Max.
Min.
Max.
Units
WRITE Cycle time
tWC
10
12
15
ns
Chip enable active time
tCW
10
10
11
ns
Address Valid to end of write
tAW
10
10
11
ns
Address setup time
tAS
0
00
ns
Address hold from end of write
tAH
0
00
ns
Write pulse width
tWP1
9
10
11
ns
Write pulse width
tWP2
10
11
12
ns
Data setup time
tDS
7
77
ns
Data hold time
tDH
0
00
ns
Write disable to output in low Z(1,3)
tLZWE
0
00
ns
Write enable to output in high Z(1,3)
tHZWE
777
ns
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDR
VCC for Retention Data
2
—
—
V
ICCDR
Data Retention Current
CE
≥ V
CC – 0.2V
VIN ≥ VCC – 0.2V
or
≤ 0.2V
VCC = 2V
—
—
500
µA
VCC = 3V
—
—
750
µA
tCDR
Chip Deselect to Data Retention Time
0
—
—
ns
tR
(3)
Operation Recovery Time
tRC
——
ns
DON'T CARE
VCC
V
V
IH
IL
t CDR
V
t R
4.5V
4.5V
Data Retention Mode
CE
DR
VDR