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SY89531LHH Datasheet(PDF) 9 Page - Micrel Semiconductor |
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SY89531LHH Datasheet(HTML) 9 Page - Micrel Semiconductor |
9 / 16 page 9 Precision Edge® SY89531L Micrel, Inc. M9999-110405 hbwhelp@micrel.com or (408) 955-1690 FUNCTIONAL DESCRIPTION At the core of the SY89531L clock synthesizer is a precision PLL driven by 14MHz to 18MHz series resonant crystal. For users who wish to supply a TTL or LVPECL clock input, please use the SY89536L. The PLL output is sent to three banks of outputs. Each bank has its own programmable frequency divider, and the design is optimized to provide very low skew between banks, and very low jitter. PLL Programming and Operation IMPORTANT: If the internal VCO will be used, VCO_SEL must be tied LOW, and ExtVCO pins can be left unconnected. The internal VCO range is 600MHz to 1000MHz, and the feedback ratio is selectable via the MSEL divider control (M3:0 pins). The VCO_SEL pin must be tied low. The feedback ratio can be changed without powering the chip down. The PLL output is fed to three banks of outputs: Bank A, Bank B, and Bank C. Banks A and C each have two differential LVPECL output pairs. Bank B has nine differential HSTL output pairs. Each bank has a separate frequency divider circuit that can be reprogrammed on the fly. The FSEL_x0:2 (where x is A, B, or C) pins control the divider value. The FSEL divider can be programmed in ratios from 2 to 18, and the outputs of Banks A, B, and C can be synchronized after programming by pulsing the OUT_SYNC pin HIGH-LOW- HIGH. Setting a value of 000 for FSEL is an output disable forcing the Q outputs to be LOW and the /Q outputs to be HIGH. Doing so will decrease power consumption by approximately 5mA per bank. To determine the correct settings for the SY89531L follow these steps: 1. Refer to the “Suggested Selections for Specific Customer Applications” section for common applications, as well as the formula used to compute the output frequency. 2. Determine the desired output frequency, such as 66MHz. 3. Choose a crystal frequency between 14MHz and 18MHz. In this example, we choose 18MHz for the crystal frequency. This results in an input/output ratio of 66/18. 4. Refer to the “Feedback Divide Select” table and the “Post-Divide Frequency Select” table to find values for MSEL and FSEL such that MSEL/FSEL equals the same 66/18 ratio. In this example, values of MSEL=44 and FSEL=12 work. 5. Make sure that XTAL (the crystal frequency) multiplied by MSEL is between 600MHz and 1000MHz. The user may need to experiment with different crystal frequencies to satisfy these requirements. ExtVCO Input Interface The flexible ExtVCO inputs are designed to accept any differential or single-ended input signal within 300mV above VCC and 300mV below ground. Do not leave unused ExtVCO inputs floating. Tie either the true or complement inputs to ground, but not both. A logic zero is achieved by connecting the complement input to ground with the true input floating. For a TTL input, see “Input Interface for ExtVCO Pins” section, Figures 5a through 5h. Input Levels LVDS, CML and HSTL differential signals may be connected directly to the ExtVCO inputs. Depending on the actual worst case voltage seen, the minimum input voltage swing varies. R2 990 Ω R2 990 Ω R1 825 Ω R1 825 Ω GND EXTVCO VCC /EXTVCO Figure 1. Simplified Input Structure |
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