MP8830

8

Rev. 1.00

TIMING DIAGRAMS

Figure 1. Clock Timing for Convert Mode

Figure 2. DC Clamp Operation

AAN

BAN

CAN

CVL

AENL

BENL

CENL

0.1%

DCL

ACLP

BCLP

CCLP

Figure 3. DAC Input and ADC Output Timing for Normal Convert Operation (CREN = 0)

CVL

AENL

BENL

CENL

AD(0-9)

OUTPUTS

DA (0-14)

INPUTS

All DAC outputs update on this edge

C Data (N-2)

A Data (N-1)

B Data (N-1)

C Data (N-1)

A (N+1)

B (N+1)

C (N+1)

Channel A output data enabled on this edge

Sample N Window