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ADL5315ACPZ-WP Datasheet(PDF) 9 Page - Analog Devices |
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ADL5315ACPZ-WP Datasheet(HTML) 9 Page - Analog Devices |
9 / 20 page ADL5315 Rev. 0 | Page 9 of 20 THEORY OF OPERATION The ADL5315 addresses the need for precision high-side monitoring of photodiode current in fiber optic systems and is useful in many nonoptical applications as well. It is optimized for use with ADI’s family of translinear logarithmic amplifiers, which take advantage of the wide input current range of the ADL5315. This arrangement allows the anode of the photo- diode to connect directly to a transimpedance amplifier for the extraction of the data stream without the need for a separate optical power monitoring tap. Figure 19 shows the basic connections for the ADL5315. ADL5315 COMM VSET NC VOLTAGE SUPPLY MIRROR CURRENT OUTPUT INPT 4 2 7 SREF 3 1 6 VPOS 5 RLIM 8 IOUT 0.01 μF 0.1 μF 2.2nF RLIM 390pF 4k Ω Figure 19. Basic Connections At the heart of the ADL5315 is a precision 1:1 current mirror with a voltage following characteristic that provides an adjustable bias voltage at the mirror input. This architecture uses a JFET input amplifier to drive the bipolar mirror and maintain stable VINPT voltage, while offering very low leakage current at the INPT pin. The current sourced by the low impedance INPT pin is mirrored and sourced by the high impedance IOUT pin. BIAS CONTROL INTERFACE The voltage at the INPT pin, VINPT, is forced to be equal to the voltage applied to VSET by the mirror-biasing loop. The VSET voltage range extends down to ground, allowing the ADL5315 to be used as a voltage-to-current converter with a single resistor from INPT to ground. This capability allows dark current to be minimized in PIN photodiode systems by maintaining a small voltage bias. The VSET control also allows VINPT to be set approximately equal to the load voltage at IOUT. Balancing the mirror voltages in this way provides inherently superior linearity over the widest current range independent of the supply voltage. Only leakage currents from the JFET op amp and ESD devices remain as significant sources of nonlinearity at very low currents. The voltage at VSET can also be used to shield the highly sensitive INPT pin and its board trace from leakage currents, because the two pins operate at approximately the same potential. Care must be taken to provide a low noise VSET signal, since voltage noise at VSET also appears at INPT and is transformed by the input compensation network into current noise. The ADL5315 provides a setpoint reference pin, SREF, which can be connected to VSET for standard 2-port mirror operation. VSREF is maintained 1.0 V below VPOS over temperature and is independent of input current. When using SREF to set the input voltage, a capacitor should be placed between SREF and ground to filter noise from SREF as well as improve power supply rejection over frequency. A value of 2.2 nF, for example, combined with the 20 kΩ output resistance at SREF, creates a pole at approximately 3 kHz. The voltage at the SREF pin can be lowered to a desired fixed value with the use of a single external resistor from SREF to ground. Mismatch between on-chip and external resistors limits the accuracy of the resultant voltage. In addition, internal clamping to protect the precision bias limits the range. Figure 20 shows an equivalent circuit model of the SREF biasing. The Schottky diode clamp protects the 50 μA current source when SREF is pulled to ground. When VSREF is 1.2 V or higher, the 50 μA current flows to the SREF pin. The current is shunted away and does not appear at the SREF pin for VSREF < 0.6 V. The transition region is between 0.6 V and 1.2 V with a large uncertainty in the pull-down current. It is recommended that a 2-resistor divider from VPOS (with no connection to SREF) or another external bias be used to bias VREF in this transition region. Equations for the SREF voltage with an external pull-down REXT follow: () V 1 V 1 kΩ 2 2 . , 0 . 0 ≥ − + = SREF POS EXT EXT SREF V V R R V V kΩ 2 6 . 0 , 0 ≤ + = SREF POS EXT EXT SREF V V R R V where the 20 kΩ is the process-dependent internal resistor. VSET VPOS CSET ADL5315 SREF 50 μA REXT 0.9V 20k Ω Figure 20. Model of SREF Bias Source with External Pull-Down |
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